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general description the max1540/max1541 dual pulse-width modulation (pwm) controllers provide the high efficiency, excellent transient response, and high dc-output accuracy nec- essary for stepping down high-voltage batteries to gen- erate low-voltage chipset and ram power supplies in notebook computers. the maxim proprietary quick-pwm controllers are free running, constant on-time with input feed forward. this configuration provides ultra-fast transient response, wide input-output (i/o) differential range, low supply current, and tight load-regulation characteris- tics. the controllers can accurately sense the inductor current across an external current-sense resistor in series with the output to ensure reliable overload and inductor saturation protection. alternatively, the con- trollers can use the synchronous rectifier itself or loss- less inductor current-sensing methods to provide overload protection with lower power dissipation. for a single step-down pwm controller with inductor- saturation protection, external-reference input voltage, and dynamically selectable output voltages, refer to the max1992/max1993 data sheet. applications notebook computers core/io supplies as low as 0.7v 0.7v to 5.5v supply rails cpu/chipset/gpu with dynamic voltage core supplies (max1541) ddr memory termination (max1541) active termination buses (max1541) features inductor-saturation protection accurate differential current-sense inputs dual ultra-high-efficiency quick-pwms with 100ns load-step response max1540 1.8v/1.2v fixed or 0.7v to 5.5v adjustable output (out1) 2.5v/1.5v fixed or 0.7v to 5.5v adjustable output (out2) fixed 5v, 100ma linear regulator max1541 external reference input (refin1) dynamically selectable output voltage?.7v to 5.5v (out1) 2.5v/1.8v fixed or 0.7v to 5.5v adjustable output (out2) optional power-good and fault blanking during transitions fixed 5v or adjustable 100ma linear regulator 1% v out accuracy over line and load 2v to 28v battery input range 170khz to 620khz selectable switching frequency overvoltage/undervoltage-protection option 1.7ms digital soft-start drives large synchronous-rectifier fets 2v ?.7% reference output separate power-good window comparators max1540/max1541 dual step-down controllers with saturation protection, dynamic output, and linear regulator ________________________________________________________________ maxim integrated products 1 thin qfn top view 32 31 30 29 28 27 26 on1 on2 csp1 csn1 fb1 out1 pgood1 25 dh1 9 10 11 12 13 14 15 csp2 csn2 fb2 out2 pgood2 dh2 lx2 16 bst2 17 18 19 20 21 22 23 gnd dl2 v+ ldoout dl1 ldoon bst1 8 7 6 5 4 3 2 ref ilim2 ilim1 v cc ton lsat skip max1540 1 ovp/uvp 24 lx1 pin configurations 19-2861; rev 0; 10/03 for pricing, delivery, and ordering information, please contact maxim/dallas direct! at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. evaluation kit available quick-pwm is a trademark of maxim integrated products, inc. * future product?ontact factory for availability. ordering information part temp range pin-package max1540 etj -40 c to +85 c 32 thin qfn 5mm x 5mm max1541 etl* -40 c to +85 c 40 thin qfn 6mm x 6mm pin configurations continued at end of data sheet.
max1540/max1541 dual step-down controllers with saturation protection, dynamic output, and linear regulator 2 _______________________________________________________________________________________ absolute maximum ratings stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. note 1: for the max1540, the gate-driver input supply (v dd ) is internally connected to the fixed 5v linear-regulator output (ldoout), and the linear-regulator input supply (ldoin) is internally connected to the battery voltage input (v+). v+, ldoon to gnd ...............................................-0.3v to +28v ldoout to gnd (max1540, note 1) ......................-0.3v to +6v ldoout to gnd (max1541, note 1) ....................-0.3v to +28v v dd to gnd (max1541, note 1) ..............................-0.3v to +6v v cc , on_ to gnd.....................................................-0.3v to +6v skip , pgood_ to gnd............................................-0.3v to +6v fb_, csp_, ilim_ to gnd.........................................-0.3v to +6v ton, ovp/uvp, lsat to gnd ...................-0.3v to (v cc + 0.3v) ref, out_ to gnd.....................................-0.3v to (v cc + 0.3v) ldoin to gnd (max1541).....................................-0.3v to +28v refin1, gate, od, fbldo to gnd (max1541).....-0.3v to +6v fblank, cc1 to gnd (max1541).............-0.3v to (v cc + 0.3v) dl_ to gnd (note 1) ..................................-0.3v to (v dd + 0.3v) csn_ to gnd ............................................................-2v to +30v dh_ to lx_..................................................-0.3v to (bst + 0.3v) lx_ to gnd................................................................-2v to +30v bst_ to lx_ ..............................................................-0.3v to +6v ref short circuit to gnd ...........................................continuous continuous power dissipation (t a = +70 c) 32-pin 5mm x 5mm thin qfn (derated 21.3mw/ c above +70 c).............................................................1702mw 40-pin 6mm x 6mm thin qfn (derated 26.3mw/ c above +70 c).............................................................2105mw operating temperature range max154_et_ ...................................................-40 c to +85 c junction temperature ......................................................+150 c storage temperature range .............................-65 c to +150 c lead temperature (soldering, 10s) .................................+300 c electrical characteristics (v+ = 15v, v cc = v dd = on1 = on2 = 5v, skip = gnd, t a = 0 c to +85 c , unless otherwise noted. typical values are at t a = +25 c.) parameter symbol conditions min typ max units input supplies (note 1) max1540: battery voltage, v+ > v ldoout 5.5 28 v in max1541: battery voltage, v+ > v ldoout 228 v bias v cc, v dd (max1541) 4.5 5.5 input voltage range v ldoin max1541: ldo input supply, v ldoin > v ldoout 4.5 28 v fb1 and fb2 forced above the regulation point, lsat = gnd 0.7 1.5 quiescent supply current (v cc )i cc fb1 and fb2 forced above the regulation point, on1 or on2 = v cc , v lsat > 0.5v 1.8 ma quiescent supply current (v dd , max1541 only) i dd fb1 and fb2 forced above the regulation point, on1 or on2 = v cc <1 5 a max1540: fb1 and fb2 forced above the regulation point, on1 or on2 = v cc , v ldoon = v+ = 28v 150 quiescent supply current (v+) i v+ max1541: on1 or on2 = v cc , v ldoon = v+ = 28v 25 40 a quiescent supply current (ldoin, max1541 only) i ldoin fb1 and fb2 forced above the regulation point, on1 or on2 = v cc , v ldoon = v+ = 28v 110 a standby supply current (v cc ) on1 = on2 = gnd, v ldoon = v+ = 28v <1 5 a
max1540/max1541 dual step-down controllers with saturation protection, dynamic output, and linear regulator _______________________________________________________________________________________ 3 electrical characteristics (continued) (v+ = 15v, v cc = v dd = on1 = on2 = 5v, skip = gnd, t a = 0 c to +85 c , unless otherwise noted. typical values are at t a = +25 c.) parameter symbol conditions min typ max units standby supply current (v dd , max1541 only) on1 = on2 = gnd, v ldoon = v+ = 28v <1 5 a max1540: on1 = on2 = gnd, ldoon = v+ = 28v, v cc = 0 or 5v 105 standby supply current (v+) max1541: on1 = on2 = gnd, ldoon = v+ = 28v, v cc = v dd = 0 or 5v <1 5 a standby supply current (ldoin, max1541 only) on1 = on2 = gnd, v ldoon = v+ = 28v 100 a shutdown supply current (v cc ) on1 = on2 = ldoon = gnd <1 5 a shutdown supply current (v dd , max1541 only) on1 = on2 = ldoon = gnd <1 5 a max1540: on1 = on2 = ldoon = gnd, v+ = 28v, v cc = 0 or 5v 415 shutdown supply current (v+) max1541: on1 = on2 = ldoon = gnd, v+ = 28v, v cc = v dd = 0 or 5v <1 5 a shutdown supply current (ldoin, max1541 only) ldoon = gnd 4 10 a pwm controllers fb1 = gnd 1.782 1.80 1.818 v out1 preset output, v+ = 5.5v to 28v, skip = v cc fb1 = v cc 1.188 1.20 1.212 max1540 main output-voltage accuracy (out1) (note 2) v fb1 adjustable output, v+ = 5.5v to 28v, skip = v cc 0.693 0.70 0.707 v fb2 = gnd 2.475 2.50 2.525 v out2 preset output, v+ = 5.5v to 28v, skip = v cc fb2 = v cc 1.485 1.50 1.515 max1540 secondary output- voltage accuracy (out2) (note 2) v fb2 adjustable output, v+ = 5.5v to 28v, skip = v cc 0.693 0.70 0.707 v max1541 main feedback- voltage accuracy (fb1) v fb1 v+ = 4.5v to 28v, skip = v cc refin1 = 0.35 x ref 0.693 0.70 0.707 v fb2 = gnd 2.475 2.50 2.525 v out2 preset output, v+ = 4.5v to 28v, skip = v cc fb2 = v cc 1.782 1.80 1.818 max1541 secondary output- voltage accuracy (out2) (note 2) v fb2 adjustable output, v+ = 4.5v to 28v, skip = v cc 0.693 0.70 0.707 v load-regulation error i load = 0 to 3a, skip = v cc 0.1 % line-regulation error v cc = 4.5v to 5.5v, v+ = 4.5v to 28v 0.25 % fb_ input bias current i fb _ -0.1 +0.1 a output adjust range 0.7 5.5 v
max1540/max1541 dual step-down controllers with saturation protection, dynamic output, and linear regulator 4 _______________________________________________________________________________________ electrical characteristics (continued) (v+ = 15v, v cc = v dd = on1 = on2 = 5v, skip = gnd, t a = 0 c to +85 c , unless otherwise noted. typical values are at t a = +25 c.) parameter symbol conditions min typ max units fb_ = gnd 70 145 350 max1540 fb_ = v cc or adjustable 50 115 220 fb1 = out1 400 700 1500 fb2 = gnd 90 170 350 out_ input resistance r out _ max1541 fb2 = v cc or adjustable 60 130 270 k ? out_ discharge mode on- resistance r d is c h arge 10 25 ? out_ synchronous-rectifier discharge-mode turn-on level 0.2 0.3 0.4 v soft-start ramp time t ss rising edge on on_ to full current limit 1.7 ms ton = gn d ( 620kh z) 149 169 190 ton = ref (485khz) 191 216 242 ton = op en ( 345kh z) 274 304 335 dh1 on-time t on1 v+ = 15v, v out1 = 1.5v (note 3) ton = v cc (235khz) 402 447 491 ns ton = gn d ( 460kh z) 201 228 256 ton = ref (355khz) 260 296 331 ton = op en ( 255kh z) 371 412 453 dh2 on-time t on2 v+ = 15v, v out2 = 1.5v (note 3) ton = v cc (170khz) 556 618 679 ns on-time tracking t on2 with respect to t on1 (note 3) 120 135 150 % minimum off-time t off ( min ) (note 3) 400 500 ns linear regulator (ldo) (note 1) 0 < i ldoout < 10ma 4.85 5.0 5.10 max1540 ldo output-voltage accuracy v ldoout on1 = on2 = gnd, v+ = 6v to 28v 0 < i ld oou t < 100m a 4.70 5.10 v 0 < i ldoout < 10ma 4.85 5.0 5.10 max1541 ldo output-voltage accuracy (fixed v ldoout ) v ldoout fbldo = on1 = on2 = gnd, v ldoin = 6v to 28v 0 < i ld oou t < 100m a 4.70 5.10 v 0 < i ldoout < 10ma 1.212 1.25 1.275 max1541 ldo feedback accuracy (adjustable v ldoout ) v fbldo fbldo = ldoout, on1 = on2 = gnd, v ldoin = 4.5v to 28v 0 < i ld oou t < 100m a 1.175 1.275 v max1541 ldo output adjust range 1.175 24 v ldoout short-circuit current 130 ma fbldo input bias current i fbldo -0.1 +0.1 a max1540: v+ - v ldoout 500 800 dropout voltage max1541: v ldoin - v ldoout 500 800 mv
max1540/max1541 dual step-down controllers with saturation protection, dynamic output, and linear regulator _______________________________________________________________________________________ 5 electrical characteristics (continued) (v+ = 15v, v cc = v dd = on1 = on2 = 5v, skip = gnd, t a = 0 c to +85 c , unless otherwise noted. typical values are at t a = +25 c.) parameter symbol conditions min typ max units reference (ref) t a = + 25 c to + 85 c 1.986 2.00 2.014 reference voltage v ref v cc = 4.5v to 5.5v, i ref = 0v t a = 0 c to +85 c 1.983 2.00 2.017 v reference load regulation ? v ref i ref = -10a to +50a -0.01 +0.01 v ref lockout voltage v ref ( uvlo ) rising edge, hysteresis = 350mv 1.95 v refin1 (max1541) voltage range v refin 0.7 v ref v refin1 (max1541) input bias current i refin1 0.01 0.05 a fault detection overvoltage trip threshold with respect to error-comparator threshold, ovp/uvp = v cc 12 16 20 % overvoltage fault-propagation delay t ovp fb forced 2% above trip threshold 10 s output undervoltage-protection trip threshold with respect to error-comparator threshold, ovp/uvp = v cc 65 70 75 % output undervoltage-protection blanking time t blank from rising edge of on_ 10 35 ms output undervoltage fault- propagation delay t uvp 10 s pgood_ lower trip threshold with respect to error-comparator threshold, hysteresis = 1% -13 -10 -7 % pgood_ upper trip threshold with respect to error-comparator threshold, hysteresis = 1% +7 +10 +13 % pgood_ propagation delay t pgood _ fb forced 2% beyond p good _ trip threshold 10 s pgood_ output low voltage i sink = 4ma 0.3 v pgood_ leakage current i pgood _ fb = ref (pgood high impedance), pgood forced to 5.5v 1a fblank = v cc 120 220 320 fblank = open 80 140 205 fault-blanking time (max1541 only) t fblank fblank = ref 35 65 95 s ldoon = v cc +150 thermal-shutdown threshold t shdn hysteresis = 10 c ldoon = gnd +160 c v cc undervoltage-lockout threshold v uvlo ( vcc ) rising edge, pwm disabled below this level, hysteresis = 20mv 4.1 4.25 4.4 v current limit ilim_ adjustment range 0.25 2 v csp_ 0 2.7 current-limit input range csn_ -0.3 +28 v csp_/csn_ input current 0.5 a
max1540/max1541 dual step-down controllers with saturation protection, dynamic output, and linear regulator 6 _______________________________________________________________________________________ dual mode is a trademark of maxim integrated products, inc. parameter symbol conditions min typ max units valley current-limit threshold (fixed) v lim _ ( val ) v csp _ - v csn _, ilim_ = v cc 45 50 55 mv v ilim _ = 250mv 15 25 35 valley current-limit threshold (adjustable) v lim _ ( val ) v csp _ - v csn _ v ilim _ = 2.00v 170 200 230 mv current-limit threshold (negative) v neg v csp _ - v csn _, skip = ilim_ = v cc , t a = +25 c -90 -65 -45 mv current-limit threshold (zero crossing) v zx with respect to valley current-limit threshold, v csp _ - v csn _, skip = gnd, ilim_ = v cc 2.5 mv lsat = v cc 180 200 220 lsat = open 157 175 193 inductor-saturation current-limit threshold with respect to valley current- limit threshold, ilim_ = v cc lsat = ref 135 150 165 % ilim_ saturation fault sink current i ilim _ ( lsat ) v csp - v csn > inductor saturation current limit, 0.25v < v ilim _ < 2.0v 468a ilim_ leakage current v csp _ - v csn _ < inductor saturation current limit 0.1 a gate drivers dh_ gate-driver on-resistance r dh bst_-lx_ forced to 5v 1.5 5 ? dl_, high state 1.5 5 dl_ gate-driver on-resistance r dl dl_, low state 0.6 3 ? dh_ gate-driver source/sink current i dh dh_ forced to 2.5v, bst_-lx_ forced to 5v 1 a dl_ gate-driver source current i dl ( source ) dl_ forced to 2.5v 1 a dl_ gate-driver sink current i dl ( sink ) dl_ forced to 2.5v 3 a dl_ rising 35 dead time t dead dh_ rising 26 ns inputs and outputs od on-resistance r od gate = v cc 10 25 ? od leakage current gate = gnd, od forced to 5.5v 1 200 na logic input threshold on1, on2, skip , gate rising edge, hysteresis = 225mv 1.2 1.7 2.2 v ldoon input trip level rising edge, hysteresis = 250mv 1.20 1.25 1.30 v logic input current on1, on2, ldoon, skip , gate -1 +1 a high 1.9 2.0 2.1 dual mode threshold voltage fb1 (max1540), fb2 (max1540/ max1541) low 0.05 0.1 0.15 v electrical characteristics (continued) (v+ = 15v, v cc = v dd = on1 = on2 = 5v, skip = gnd, t a = 0 c to +85 c , unless otherwise noted. typical values are at t a = +25 c.)
max1540/max1541 dual step-down controllers with saturation protection, dynamic output, and linear regulator _______________________________________________________________________________________ 7 electrical characteristics (continued) (v+ = 15v, v cc = v dd = on1 = on2 = 5v, skip = gnd, t a = 0 c to +85 c , unless otherwise noted. typical values are at t a = +25 c.) parameter symbol conditions min typ max units high v cc - 0.4v open 3.15 3.85 ref 1.65 2.35 four-level input logic levels ton, ovp/uvp, lsat, skip , fblank low 0.5 v four-level logic input current ton, ovp/uvp, lsat, skip , fblank forced to gnd or v cc -3 +3 a electrical characteristics (v+ = 15v, v cc = v dd = on1 = on2 = 5v, skip = gnd, t a = -40 c to +85 c , unless otherwise noted.) (note 4) parameter symbol conditions min max units input supplies (note 1) max1540: battery voltage, v+ > v ldoout 5.5 28 v in max1541: battery voltage, v+ > v ldoout 228 v bias v cc, v dd (max1541) 4.5 5.5 input voltage range v ldoin max1541: ldo input supply, v ldoin > v ldoout 4.5 28 v fb1 and fb2 forced above the regulation point, lsat = gnd 1.5 quiescent supply current (v cc )i cc fb1 and fb2 forced above the regulation point, on1 or on2 = v cc , v lsat > 0.5v 1.8 ma quiescent supply current (v dd , max1541 only) i dd fb1 and fb2 forced above the regulation point, on1 or on2 = v cc 5a max1540: fb1 and fb2 forced above the regulation point, on1 or on2 = v cc , v ldoon = v+ = 28v 150 quiescent supply current (v+) i v+ max1541: on1 or on2 = v cc , v ldoon = v+ = 28v 40 a quiescent supply current (ldoin, max1541 only) i ldoin fb1 and fb2 forced above the regulation point, on1 or on2 = v cc , v ldoon = v+ = 28v 110 a standby supply current (v dd ) on1 = on2 = gnd, v ldoon = v+ = 28v 5 a standby supply current (v dd , max1541 only) on1 = on2 = gnd, v ldoon = v+ = 28v 5 a max1540: on1 = on2 = gnd, ldoon = v+ = 28v, v cc = 0 or 5v 105 standby supply current (v+) max1541: on1 = on2 = gnd, ldoon = v+ = 28v, v cc = v dd = 0 or 5v 5 a standby supply current (ldoin, max1541 only) on1 = on2 = gnd, v ldoon = v+ = 28v 100 a
max1540/max1541 dual step-down controllers with saturation protection, dynamic output, and linear regulator 8 _______________________________________________________________________________________ electrical characteristics (continued) (v+ = 15v, v cc = v dd = on1 = on2 = 5v, skip = gnd, t a = -40 c to +85 c , unless otherwise noted.) (note 4) parameter symbol conditions min max units shutdown supply current (v cc ) on1 = on2 = ldoon = gnd 5 a shutdown supply current (v dd , max1541 only) on1 = on2 = ldoon = gnd 5 a max1540: on1 = on2 = ldoon = gnd, v+ = 28v, v cc = 0 or 5v 15 shutdown supply current (v+) max1541: on1 = on2 = ldoon = gnd, v+ = 28v, v cc = v dd = 0 or 5v 5 a shutdown supply current (ldoin, max1541 only) ldoon = gnd 10 a pwm controllers fb1 = gnd 1.773 1.827 v out1 preset output, v+ = 5.5v to 28v, skip = v cc fb1 = v cc 1.182 1.218 max1540 main output-voltage accuracy (out1) (note 2) v fb1 adjustable output, v+ = 5.5v to 28v, skip = v cc 0.689 0.711 v fb2 = gnd 2.462 2.538 v out2 preset output, v+ = 5.5v to 28v, skip = v cc fb2 = v cc 1.477 1.523 max1540 secondary output- voltage accuracy (out2) (note 2) v fb2 adjustable output, v+ = 5.5v to 28v, skip = v cc 0.689 0.711 v refin1 = 0.35 x ref 0.689 0.711 max1541 main feedback voltage accuracy (fb1) v fb1 v+ = 4.5v to 28v, skip = v cc refin1 = ref 1.97 2.03 v fb2 = gnd 2.462 2.538 v out2 preset output, v+ = 4.5v to 28v, skip = v cc fb2 = v cc 1.773 1.827 max1541 secondary output- voltage accuracy (out2) (note 2) v fb2 adjustable output, v+ = 4.5v to 28v, skip = v cc 0.689 0.711 v ton = g n d ( 620kh z) 149 190 ton = re f ( 485kh z) 191 242 ton = op en ( 345kh z) 274 335 dh1 on-time (note 3) t on1 v+ = 15v, v out1 = 1.5v ton = v cc ( 235kh z) 402 491 ns ton = g n d ( 460kh z) 201 256 ton = re f ( 355kh z) 260 331 ton = op en ( 255kh z) 371 453 dh2 on-time (note 3) t on2 v+ = 15v, v out2 = 1.5v ton = v cc ( 170kh z) 556 679 ns on-time tracking t on2 with respect to t on1 (note 3) 118 152 % minimum off-time t off ( min ) (note 3) 500 ns linear regulator (ldo) (note 1) 0 < i ldoout < 10ma 4.85 5.10 max1540 ldo output-voltage accuracy v ldoout on1 = on2 = gnd, v+ = 6v to 28v 0 < i l d oou t < 100m a 4.65 5.10 v
max1540/max1541 dual step-down controllers with saturation protection, dynamic output, and linear regulator _______________________________________________________________________________________ 9 electrical characteristics (continued) (v+ = 15v, v cc = v dd = on1 = on2 = 5v, skip = gnd, t a = -40 c to +85 c , unless otherwise noted.) (note 4) parameter symbol conditions min max units 0 < i ldoout < 10ma 4.85 5.10 max1541 ldo output-voltage accuracy (fixed v ldoout ) v ldoout fbldo = on1 = on2 = gnd, v ldoin = 6v to 28v 0 < i l d oou t < 100m a 4.65 5.10 v 0 < i ldoout < 10ma 1.212 1.275 max1541 ldo feedback accuracy (adjustable v ldoout ) v fbldo fbldo = ldoout, on1 = on2 = gnd, v ldoin = 4.5v to 28v 0 < i l d oou t < 100m a 1.175 1.275 v max1540: v+ - v ldoout 800 dropout voltage max1541: v ldoin - v ldoout 800 mv reference (ref) reference voltage v ref v cc = 4.5v to 5.5v, i ref = 0 1.98 2.02 v refin1 input bias current i refin1 0.05 a fault detection overvoltage trip threshold with respect to error-comparator threshold, ovp/uvp = v cc 10 21 % output undervoltage-protection trip threshold with respect to error-comparator threshold, ovp/uvp = v cc 64 76 % pgood_ lower trip threshold with respect to error-comparator threshold, hysteresis = 1% -14 -5 % pgood_ upper trip threshold with respect to error-comparator threshold, hysteresis = 1% +5 +14 % pgood_ output low voltage i sink = 4ma 0.3 v v cc undervoltage-lockout threshold v uvlo ( vcc ) rising edge, pwm disabled below this level, hysteresis = 20mv 4.1 4.4 v current limit csp_ 0 2.7 current-limit input range csn_ -0.3 +28.0 v valley current-limit threshold (fixed) v lim _ ( val ) v csp _ - v csn _, ilim_ = v cc 40 60 mv valley current-limit threshold (adjustable) v lim _ ( val ) v csp _ - v csn _, v ilim _ = 2.00v 160 240 mv inputs and outputs logic input threshold on1, on2, skip , gate, rising edge, hysteresis = 225mv 1.2 2.2 v ldoon input trip level rising edge, hysteresis = 250mv 1.2 1.3 v high 1.9 2.1 dual mode threshold voltage fb1 (max1540), fb2 (max1540/max1541) low 0.05 0.15 v
max1540/max1541 dual step-down controllers with saturation protection, dynamic output, and linear regulator 10 ______________________________________________________________________________________ electrical characteristics (continued) (v+ = 15v, v cc = v dd = on1 = on2 = 5v, skip = gnd, t a = -40 c to +85 c , unless otherwise noted.) (note 4) parameter symbol conditions min max units high v cc - 0.4v open 3.15 3.85 ref 1.65 2.35 four-level input logic levels ton, ovp/uvp, lsat, skip , fblank low 0.5 v note 1: for the max1540, the gate-driver input supply (v dd ) is internally connected to the fixed 5v linear-regulator output (ldoout), and the linear-regulator input supply (ldoin) is internally connected to the battery voltage input (v+). note 2: when the inductor is in continuous conduction, the output voltage has a dc regulation level higher than the error-comparator threshold by 50% of the ripple. in discontinuous conduction ( skip = gnd, light load), the output voltage has a dc regulation level higher than the trip level by approximately 1.5% due to slope compensation. note 3: on-time and off-time specifications are measured from 50% point to 50% point at the dh_ pin with lx_ = gnd, vbst_ = 5v, and a 250pf capacitor connected from dh_ to lx_. actual in-circuit times may differ due to mosfet switching speeds. note 4: specifications to -40 c are guaranteed by design, not production tested. out2 efficiency vs. load current (v out2 = 2.5v) max1540 toc01 load current (a) efficiency (%) 1 0.1 55 60 65 70 75 80 85 90 95 100 50 0.01 10 skip = gnd skip = v cc v in = 7v v in = 12v v in = 20v 2.5v output voltage (out2) vs. load current max1540 toc02 load current (a) output voltage (v) 4 3 2 1 2.49 2.50 2.51 2.52 2.53 2.54 2.55 2.48 05 skip = gnd skip = v cc out1 efficiency vs. load current (v out1 = 1.0v) max1540 toc03 load current (a) efficiency (%) 1 0.1 55 60 65 70 75 80 85 90 95 100 50 0.01 10 skip = gnd skip = v cc v in = 7v v in = 12v v in = 20v typical operating characteristics (max1541 circuit of figure 12, v in = 12v, v dd = v cc = 5v, skip = gnd, ton = ref, t a = +25 c, unless otherwise noted.)
max1540/max1541 dual step-down controllers with saturation protection, dynamic output, and linear regulator ______________________________________________________________________________________ 11 1.0v output voltage (out1) vs. load current max1540 toc04 load current (a) output voltage (v) 4 3 1 2 0.99 1.00 1.01 1.02 0.98 05 skip = gnd skip = v cc out2 switching frequency vs. load current (v out2 = 2.5v) max1540 toc05 load current (a) switching frequency (khz) 4 3 2 1 100 200 300 400 500 600 0 05 skip = gnd skip = v cc out1 switching frequency vs. load current (v out1 = 1.0v) max1540 toc06 load current (a) switching frequency (khz) 4 3 2 1 100 200 300 400 500 600 0 05 skip = gnd skip = v cc switching frequency vs. input voltage max1540 toc07 input voltage (v) switching frequency (khz) 24 20 16 12 8 4 250 300 350 400 450 200 028 4a load no load 2.5v output skip = v cc maximum output current vs. input voltage max1540 toc08 input voltage ( v ) maximum output current (a) 24 20 12 16 8 4 4.2 4.4 4.6 4.8 5.0 5.2 5.4 5.6 5.8 6.0 4.0 028 2.5v output no-load supply current vs. input voltage (forced-pwm operation) max1540 toc09 input voltage (v) supply current (ma) 24 20 16 12 8 4 4 8 12 16 20 0 028 i bias i in skip = on1 = on2 = v cc no-load supply current vs. input voltage (pulse-skipping operation) max1540 toc10 input voltage (v) supply current (ma) 24 20 16 12 8 4 0.2 0.4 0.6 0.8 1.0 1.2 1.4 0 028 skip = gnd on1 = on2 = v cc i bias i in 2.0v reference load regulation max1540 toc11 reference load current ( a) reference voltage deviation (mv) 100 80 60 40 20 0 -3 -2 -1 0 1 2 3 4 -4 -20 reference distribution max1540 toc12 reference voltage (v) sample percentage (%) 2.005 2.000 1.995 10 20 30 40 50 0 1.990 2.010 sample size = 50 typical operating characteristics (continued) (max1541 circuit of figure 12, v in = 12v, v dd = v cc = 5v, skip = gnd, ton = ref, t a = +25 c, unless otherwise noted.)
max1540/max1541 dual step-down controllers with saturation protection, dynamic output, and linear regulator 12 ______________________________________________________________________________________ typical operating characteristics (continued) (max1541 circuit of figure 12, v in = 12v, v dd = v cc = 5v, skip = gnd, ton = ref, t a = +25 c, unless otherwise noted.) linear-regulator output (ldoout) vs. load current max1540 toc13 ldo load current (ma) ldo output voltage (v) 80 60 20 40 3.22 3.24 3.26 3.28 3.30 3.32 3.34 3.36 3.20 0 100 v ldoin = 5v v ldoin = 12v startup waveform (heavy load) max1540 toc14 3.3v 0 2.5v 0 b d c a 400 s/div 4a 2a 0 0 a. on2, 5v/div b. inductor current, 2a/div 0.5 ? load c. out2, 2v/div d. pgood2, 5v/div startup waveform (light load) max1540 toc15 3.3v 0 2.5v 0 b d c a 200 s/div 4a 2a 0 0 a. on2, 5v/div b. inductor current, 2a/div 100 ? load c. out2, 2v/div d. pgood2, 5v/div shutdown waveform (discharge mode disabled) max1540 toc16 3.3v 0 5v 0 b d c a 10ms/div 2.5v 0 0 0 a. on2, 5v/div b. out2, 2v/div c. inductor current, 2a/div 100 ? load, ovp/uvp = ref or gnd d. dl2, 5v/div e. pgood2, 5v/div 5v e
max1540/max1541 dual step-down controllers with saturation protection, dynamic output, and linear regulator ______________________________________________________________________________________ 13 typical operating characteristics (continued) (max1541 circuit of figure 12, v in = 12v, v dd = v cc = 5v, skip = gnd, ton = ref, t a = +25 c, unless otherwise noted.) shutdown waveform (discharge mode enabled) max1540 toc17 3.3v 0 5v 0 b d c a 1ms/div 2.5v 0 0 0 a. on2, 5v/div b. out2, 2v/div c. inductor current, 2a/div 100 ? load, ovp/uvp = v cc or open d. dl2, 5v/div e. pgood2, 5v/div 5v e 2.5v output load transient (forced pwm) max1540 toc18 4a 0 4a 0 b d c a 40 s/div 2.5v 2.4v 2.6v a. i out2 = 0 to 4a, 5a/div b. v out2 = 2.5v, 100mv/div skip = v cc c. inductor current, 5a/div d. lx2, 10v/div 12v 0 2.5v output load transient (pulse skipping) max1540 toc19 4a 0 4a 0 b d c a 40 s/div 2.5v 2.4v 2.6v a. i out2 = 0.1a to 4a, 5a/div b. v out2 = 2.5v, 100mv/div skip = gnd c. inductor current, 5a/div d. lx2, 10v/div 12v 0 linear-regulator load transient max1540 toc20 100ma 0 b a 100 s/div 3.3v 3.2v 3.4v a. i ldoout = 1ma to 100ma, 50ma/div b. v ldoout = 3.3v, 100mv/div skip = gnd
max1540/max1541 dual step-down controllers with saturation protection, dynamic output, and linear regulator 14 ______________________________________________________________________________________ typical operating characteristics (continued) (max1541 circuit of figure 12, v in = 12v, v dd = v cc = 5v, skip = gnd, ton = ref, t a = +25 c, unless otherwise noted.) linear-regulator line transient max1540 toc21 20v 10v 20v 10v 3.8v 3.3v 2.8v c a b 200 s/div a. input (v in ), 10v/div b. ldoin (10v to 20v), 10v/div c. ldoout (3.3v), 500mv/div 20ma load output overload (uvp disabled) max1540 toc22 20a 0 2.5v 10a b d c a 40 s/div 0 5a 0 5v a. load (0 to 150m ? ), 10a/div b. inductor current, 10a/div ovp/uvp = open or gnd c. 2.5v output, 2v/div d. pgood2, 5v/div 0 output overload (uvp enabled) max1540 toc23 20a 0 2.5v 10a b d c a 20 s/div 0 5a 0 5v a. load (0 to 150m ? ), 10a/div b. inductor current, 10a/div c. dl2, 5v/div ovp/uvp = v cc or ref d. 2.5v output, 2v/div e. pgood2, 5v/div e 0 5v inductor-saturation protection (lsat disabled) max1540 toc24 0 2.5v b d c a 20 s/div 5a 7.5a a. i out2 = 0 to 5a, 5a/div b. 2.5v output, 200mv/div lsat = gnd, l = 3.3 h 3.5a c. ilim, 100mv/div d. inductor current, 5a/div 0.67v 0
max1540/max1541 dual step-down controllers with saturation protection, dynamic output, and linear regulator ______________________________________________________________________________________ 15 typical operating characteristics (continued) (max1541 circuit of figure 12, v in = 12v, v dd = v cc = 5v, skip = gnd, ton = ref, t a = +25 c, unless otherwise noted.) inductor-saturation protection ( ? v ilim = 200mv) max1540 toc25 0 2.5v b d c a 20 s/div 5a 7.5a a. i out2 = 0 to 5a, 5a/div b. 2.5v output, 200mv/div lsat = ref, l = 3.3 h 3.5a c. ilim, 200mv/div d. inductor current, 5a/div 0.67v 0 0.47v inductor-saturation protection ( ? v ilim = 400mv) max1540 toc26 0 2.5v 1.5v b d c a 20 s/div 5a 5a a. i out2 = 0 to 5a, 5a/div b. 2.5v output, 1v/div c. pgood, 5v/div lsat = ref, l = 3.3 h 3.5a d. ilim, 400mv/div e. inductor current, 5a/div 5v 0 0.67v e 0.27v max1541 dynamic output-voltage transition (c refin1 = 100pf) max1540 toc27 -5a 1.5v b d c a 40 s/div 5a 5a a. gate, 5v/div b. out1 (1.0v to 1.5v), 0.5v/div c. refin1, 0.5v/div 200ma load, skip = gnd d. pgood1, 5v/div e. inductor current, 5a/div 1.5v 0 1v e 5v 0 max1541 dynamic output-voltage transition (c refin1 = 1nf) max1540 toc28 -5a 1.5v b d c a 100 s/div 5a 5a a. gate, 5v/div b. out1 (1.0v to 1.5v), 0.5v/div c. refin1, 0.5v/div 200ma load, skip = gnd d. pgood1, 5v/div e. inductor current, 5a/div 1.5v 0 1v e 5v 0
max1540/max1541 dual step-down controllers with saturation protection, dynamic output, and linear regulator 16 ______________________________________________________________________________________ pin max1540 max1541 name function 1 1 ovp/uvp overvoltage/undervoltage protection and discharge-mode control input. this four- level logic input selects between various output fault-protection options (table 7) by selectively enabling ovp protection and uvp protection. when enabled, the ovp limit defaults at 116% of the nominal output voltage, and the uvp limit defaults at 70% of the nominal output voltage. discharge mode is enabled when ovp protection is also enabled. connect ovp/uvp to the following pins for the desired function: v cc = enable ovp and discharge mode, enable uvp. open = enable ovp and discharge mode, disable uvp. ref = disable ovp and discharge mode, enable uvp. gnd = disable ovp and discharge mode, disable uvp. see the fault protection and shutdown and output discharge sections. 22 skip pulse-skipping control input. this four-level logic input enables or disables the light- load pulse-skipping operation of each output: v cc = out1 and out2 in forced-pwm mode. open = out1 in forced-pwm mode, out2 in pulse-skipping mode. ref = out1 in pulse-skipping mode, out2 in forced-pwm mode. gnd = out1 and out2 in pulse-skipping mode. 3 3 lsat inductor-saturation control input. this four-level logic input sets the inductor-current saturation limit as a multiple of the valley current-limit threshold set by ilim, or disables the function if not required. connect lsat to the following pins to set the saturation current limit: v cc = 2 x i lim(val) open = 1.75 x i lim(val) ref = 1.5 x i lim(val) gnd = disable lsat protection see the inductor saturation limit and setting the current limit sections. 4 4 ton on-time selection control input. this four-level logic input sets the k-factor value used to determine the dh_ on-time (see the on-time one-shot section). connect to analog ground (gnd), ref, or v cc ; or leave ton unconnected to select the following nominal switching frequencies: v cc = 235khz (out1) / 170khz (out2) open = 345khz (out1) / 255khz (out2) ref = 485khz (out1) / 355khz (out2) gnd = 620khz (out1) / 460khz (out2) 55v cc analog supply input. connect to the system supply voltage (+4.5v to +5.5v) through a series 20 ? resistor. bypass v cc to analog ground with a 1f or greater ceramic capacitor. 6 gate buffered n-channel mosfet gate input. a logic low on gate turns off the internal mosfet so od appears as high impedance. a logic high on gate turns on the internal mosfet, pulling od to ground. 7 cc1 integrator capacitor connection for controller 1. connect a 47pf to 470pf (47pf typ) capacitor from cc1 to analog ground (gnd) to set the integration time constant for the main max1541 controller (out1). pin description
max1540/max1541 dual step-down controllers with saturation protection, dynamic output, and linear regulator ______________________________________________________________________________________ 17 pin max1540 max1541 name function 6 8 ilim1 valley current-limit threshold adjustment for controller 1. the valley current-limit threshold defaults to 50mv if ilim1 is tied to v cc . in adjustable mode, the valley current-limit threshold across csp1 and csn1 is precisely 1/10 the voltage seen at ilim1 over a 250mv to 2.5v range. the logic threshold for switchover to the 50mv default value is approximately v cc - 1v. when the inductor-saturation protection threshold is exceeded, ilim1 sinks 6a. see the current-limit protection section. 7 9 ilim2 valley current-limit threshold adjustment for controller 2. the valley current-limit threshold defaults to 50mv if ilim2 is tied to v cc . in adjustable mode, the valley current-limit threshold across csp2 and csn2 is precisely 1/10th the voltage seen at ilim2 over a 250mv to 2.5v range. the logic threshold for switchover to the 50mv default value is approximately v cc - 1v. when the inductor-saturation protection threshold is exceeded, ilim2 sinks 6a. see the current-limit protection section. 8 10 ref 2.0v reference voltage output. bypass ref to analog ground with a 0.1f or greater ceramic capacitor. the reference can source up to 50a for external loads. loading ref degrades output voltage accuracy according to the ref load-regulation error. the reference is disabled when the max1540/max1541 are shut down. 11 refin1 external reference input for controller 1. refin1 sets the main feedback regulation voltage (v fb1 = v refin1 ) of the max1541. 12 od open-drain output. controlled by gate. 9 13 csp2 positive current-sense input for controller 2. connect to the positive terminal of the current-sense element. figure 14 and table 9 describe several current-sensing options. the pwm controller does not begin a cycle unless the current sensed is less than the valley current-limit threshold programmed at ilim2. 10 14 csn2 negative current-sense input for controller 2. connect to the negative terminal of the current-sense element. figure 14 and table 9 describe several current-sensing options. the pwm controller does not begin a cycle unless the current sensed is less than the valley current-limit threshold programmed at ilim2. 11 15 fb2 feedback input for controller 2: m ax 1540: c onnect to v c c for a + 1.5v fi xed outp ut or to anal og g r ound ( g n d ) for a + 2.5v fi xed outp ut. for an ad j ustab l e outp ut ( 0.7v to 5.5v ) , connect fb2 to a r esi sti ve d i vi d er fr om ou t2. the fb2 r eg ul ati on l evel i s + 0.7v . m ax 1541: c onnect to v c c for a + 1.8v fi xed outp ut or to anal og g r ound ( g n d ) for a + 2.5v fi xed outp ut. for an ad j ustab l e outp ut ( 0.7v to 5.5v ) , connect fb2 to a r esi sti ve d i vi d er fr om ou t2. the fb2 r eg ul ati on l evel i s + 0.7v . 12 16 out2 output voltage-sense connection for controller 2. connect directly to the positive terminal of the output capacitors as shown in the standard application circuits (figures 1 and 12). out2 senses the output voltage to determine the on-time for the high-side switching mosfet. out2 also serves as the feedback input when using the preset internal output voltages as shown in figure 10. when discharge mode is enabled by ovp/uvp, the output capacitor is discharged through an internal 10 ? resistor connected between out2 and ground. pin description (continued)
max1540/max1541 dual step-down controllers with saturation protection, dynamic output, and linear regulator 18 ______________________________________________________________________________________ pin max1540 max1541 name function 13 17 pgood2 open-drain power-good output. pgood2 is low when the output voltage is more than 10% (typ) above or below the normal regulation point, during soft-start, and in shutdown. after the soft-start circuit has terminated, pgood2 becomes high impedance if the output is in regulation. 14 18 dh2 high-side gate-driver output for controller 2. dh2 swings from lx2 to bst2. 15 19 lx2 inductor connection for controller 2. connect to the switched side of the inductor. lx2 serves as the lower supply rail for the dh2 high-side gate driver. 16 20 bst2 boost flying-capacitor connection for controller 2. connect to an external capacitor and diode as shown in figure 8. an optional resistor in series with bst2 allows the dh2 pullup current to be adjusted. 17 21 gnd analog and power ground. connect backside pad to gnd. 18 22 dl2 low-side gate-driver output for controller 2. dl2 swings from gnd to ldoout (max1540) or gnd to v dd (max1541). 19 23 v+ battery voltage input. the controller uses v+ to set the on-time one-shot timing. the dh on-time is inversely proportional to input voltage over a range of 2v to 28v. for the max1540, v+ also serves as the linear-regulator input supply. 24 ldoin internal linear-regulator input supply. connect to v+ or a voltage source from 4.5v to 28v through a 1 ? resistor. bypass ldoin to gnd with a 4.7f or greater capacitor. for the max1540, ldoin is internally connected to v+. 25 v dd max1541 supply voltage input for the dl_ gate driver. connect to the system supply voltage (+4.5v to +5.5v). bypass v dd to power ground with a 1f or greater ceramic capacitor. for the max1540, ldoout supplies the dl_ gate drivers (v dd = ldoout). 20 26 ldoout linear regulator output. bypass ldoout with a 1f or greater capacitor per 5ma of load (internal and external), with a minimum of 4.7f. for the max1540, ldoout powers the dl_ gate drivers (v dd internally connected to ldoout). 27 fbldo feedback input for the linear regulator. connect to gnd for a fixed 5v output. for an adjustable output (1.25v to v ldoin - 0.6v), connect fbldo to a resistive voltage- divider from ldoout to analog ground (gnd). the fbldo regulation voltage is +1.25v. for the max1540, fbldo is internally connected to gnd for a fixed 5v output. 21 28 dl1 low-side gate-driver output for controller 1. dl1 swings from gnd to ldoout (max1540) or gnd to v dd (max1541). 22 29 ldoon linear-regulator enable input. for automatic startup, connect to v+ or ldoin (max1541). connect to gnd to shut down the linear regulator. 23 30 bst1 boost flying-capacitor connection for controller 1. connect to an external capacitor and diode as shown in figure 8. an optional resistor in series with bst1 allows the dh1 pullup current to be adjusted. pin description (continued)
max1540/max1541 dual step-down controllers with saturation protection, dynamic output, and linear regulator ______________________________________________________________________________________ 19 pin max1540 max1541 name function 24 31 lx1 inductor connection for controller 1. connect to the switched side of the inductor. lx1 serves as the lower supply rail for the dh1 high-side gate driver. 25 32 dh1 high-side gate-driver output for controller 1. dh1 swings from lx1 to bst1. 26 33 pgood1 open-drain power-good output. pgood1 is low when the output voltage is more than 10% (typ) above or below the normal regulation point, during soft-start, and in shutdown. after the soft-start circuit has terminated, pgood1 becomes high impedance if the output is in regulation. for the max1541, pgood1 is blanked forced high-impedance state when fblank is enabled and the controller detects a transition on gate. 27 34 out1 output voltage-sense connection for controller 1. connect directly to the positive terminal of the output capacitors as shown in the standard application circuits (figures 1 and 12). out1 senses the output voltage to determine the on-time for the high-side switching mosfet. for the max1540, out1 also serves as the feedback input when using the preset internal output voltages as shown in figure 10. when discharge mode is enabled by ovp/uvp, the output capacitor is discharged through an internal 10 ? resistor connected between out1 and ground. 28 35 fb1 feedback input for controller 1: m ax 1540: c onnect to v c c for a + 1.2v fi xed outp ut or to anal og g r ound ( g n d ) for a + 1.8v fi xed outp ut. for an ad j ustab l e outp ut ( 0.7v to 5.5v ) , connect fb1 to a r esi sti ve d i vi d er fr om ou t1. the fb1 r eg ul ati on l evel i s + 0.7v . m ax 1541: the fb1 r eg ul ati on l evel i s set b y the vol tag e at re fin 1. 29 36 csn1 negative current-sense input for controller 1. connect to the negative terminal of the current-sense element. figure 14 and table 9 describe several current-sensing options. the pwm controller does not begin a cycle unless the current sensed is less than the valley current-limit threshold programmed at ilim1. 30 37 csp1 positive current-sense input for controller 1. connect to the positive terminal of the current-sense element. figure 14 and table 9 describe several current-sensing options. the pwm controller does not begin a cycle unless the current sensed is less than the valley current-limit threshold programmed at ilim1. 38 fblank fault-blanking control input. this four-level logic input enables or disables fault blanking, and sets the forced-pwm operation time (t fblank ). when fault blanking is enabled, pgood1 and the ovp/uvp protection for controller 1 are blanked for the selected time period after the max1541 detects a transition on gate. additionally, controller 1 enters forced-pwm mode for the duration of t fblank anytime gate changes states. connect fblank as follows: v cc = 220s t fblank , fault blanking enabled. open = 140s t fblank , fault blanking enabled. ref = 65s t fblank , fault blanking enabled. gnd = 140s t fblank , fault blanking disabled. see the electrical characteristics table for the t fblank limits. pin description (continued)
max1540/max1541 dual step-down controllers with saturation protection, dynamic output, and linear regulator 20 ______________________________________________________________________________________ pin max1540 max1541 name function 31 39 on2 out2 enable input. pull on2 to gnd to shut down controller 2 (out2). connect to v cc for normal operation. when discharge mode is enabled by ovp/uvp, the output is discharged through a 10 ? resistor between out2 and gnd, and dl2 is forced high after v out2 drops below 0.3v. when discharge mode is disabled by ovp/uvp, out2 remains a high-impedance input and dl2 is forced low so lx2 also appears as a high impedance. a rising edge on on1 or on2 clears the fault-protection latch. 32 40 on1 out1 enable input. pull on1 to gnd to shut down controller 1 (out1). connect to v cc for normal operation. when discharge mode is enabled by ovp/uvp, the output is discharged through a 10 ? resistor between out1 and gnd, and dl1 is forced high after v out1 drops below 0.3v. when discharge mode is disabled by ovp/uvp, out1 remains a high-impedance input and dl1 is forced low so lx1 also appears as high impedance. a rising edge on on1 or on2 clears the fault-protection latch. pin description (continued) table 1. component selection for standard applications max1540 max1541 component pwm1 pwm2 pwm1 pwm2 input voltage (v in ) 7v to 24v 7v to 24v 7v to 24v 7v to 24v output voltage (v out _) 1.8v 2.5v 1.0v/1.5v 2.5v load current (i out _) 4a 8a 4a 4a s w i tchi ng fr eq uency ( f s w _) ton = ref (485khz) ton = ref (355khz) ton = ref (485khz) ton = ref (355khz) input capacitor (c in ) (2) 10f, 25v taiyo yuden tmk432bj106km (2) 4.7f, 25v taiyo yuden tmk325bj475km output capacitor (c out _) 220f, 6.3v, 12m ? sanyo poscap 6tpd220m 330f, 4v, 12m ? sanyo poscap 4tpd330m 470f, 4v, 10m ? sanyo poscap 4tpd470m 220f, 6.3v, 12m ? sanyo poscap 6tpd220m high-side mosfet (n h _) 35m ? , 30v fairchild 1/2 fds6982s 20m ? , 30v fairchild fds6690 35m ? , 30v fairchild 1/2 fds6982s 35m ? , 30v fairchild 1/2 fds6982s low-side mosfet (n l _) 22m ? , 30v fairchild 1/2 fds6982s 12.5m ? , 30v fairchild fds6670s 22m ? , 30v fairchild 1/2 fds6982s 22m ? , 30v fairchild 1/2 fds6982s low-side schottky (d l _) (if needed) 1a, 30v schottky nihon ep10qs03l 1a, 30v schottky nihon ep10qs03l 1a, 30v schottky nihon ep10qs03l 1a, 30v schottky nihon ep10qs03l inductor (l_) 2.5h, 6.2a, 15m ? sumida cdep105(h)-2r5 2.2h, 10a, 4.4m ? sumida cdep105(l)-2r2 1.8h, 9.0a, 6.2m ? sumida cdep105(s)-1r8 4.3h, 6.8a, 8.7m ? sumida cdep105(l)-4r3 r sense_ 15m ? 1%, 0.5w irc lr2010-01-r015f or dale wsl-2010-r015f 5m ? 1%, 0.5w irc lr2010-01-r005f or dale wsl-2010-r005f 15m ? 1%, 0.5w irc lr2010-01-r015f or dale wsl-2010-r015f 15m ? 1%, 0.5w irc lr2010-01-r015f or dale wsl-2010-r015f
max1540/max1541 dual step-down controllers with saturation protection, dynamic output, and linear regulator ______________________________________________________________________________________ 21 figure 1. max1540 standard application circuit max1540 +5v bias supply output 1 1.8v, 4a (max) ref (485khz/355khz) power ground analog ground power-good on off open (i lim(val) x 1.75) output 2 2.5v, 8a (max) input (v in )* 7v to 20v ldoout dh1 bst1 lx1 csp1 dl1 csn1 out1 fb1 skip ton ref ilim1 ilim2 pgood2 pgood1 v cc on2 on1 ldoon lsat ovp/uvp fb2 out2 csn2 csp2 gnd dl2 lx2 bst2 dh2 v+ r7 100k ? r6 100k ? c2 1 f r1 20 ? c out2 330 f r cs2 5m ? l2 2.2 h d l2 d l1 r cs1 15m ? c out1 220 f l1 2.5 h n l1 n l2 n h1 n h2 c bst2 0.1 f c bst1 0.1 f d bst d bst c1 22 f c ref 0.22 f c3 470pf c4 470pf r2 100k ? r3 49.9k ? r4 200k ? r5 49.9k ? see table 1 for component specifications. *lower input voltages require additional input capacitance. +5v bias supply c in (2) 10 f
max1540/max1541 standard application circuits the max1540 standard application circuit (figure 1) generates a 1.8v and 2.5v rail for general-purpose use in a notebook computer. the max1541 standard application circuit (figure 12) generates a dynamically adjustable output voltage (out1), typical of a graphics- processor core requirement, and a fixed 2.5v output (out2). see table 1 for component selections. table 2 lists the component manufacturers. detailed description the max1540/max1541 provide three independent out- puts with independent enable controls. they contain two quick-pwm step-down controllers ideal for low-voltage power supplies for notebook computers, and a 100ma linear regulator. maxim s proprietary quick-pwm pulse- width modulators in the max1540/ max1541 are specifi- cally designed for handling fast load steps while maintaining a relatively constant operating frequency and inductor operating point over a wide range of input volt- ages. the quick-pwm architecture circumvents the poor load-transient timing problems of fixed-frequency current- mode pwms, while also avoiding the problems caused by widely varying switching frequencies in conventional constant-on-time and constant-off-time pwm schemes. the max1540 linear regulator draws power from the battery voltage and generates a preset 5v, which can be used to bootstrap the buck controllers for automatic startup. the max1541 s linear regulator can be con- nected to any input source from 4.5v to 28v to gener- ate an adjustable output voltage as low as 1.25v, or as high as the input source with 600mv of dropout. single-stage buck conversion allows the max1540/ max1541 to directly step down high-voltage batteries for the highest possible efficiency. alternatively, two- stage conversion (stepping down from another system supply rail instead of the battery at a higher switching frequency) allows the minimum possible physical size. the max1540 generates chipset, dynamic random- access memory (dram), cpu i/o, or other low-voltage supplies down to 0.7v. the max1541 powers chipsets and graphics processor cores that require dynamically adjustable output voltages, or generates the active ter- mination bus that must track the input reference. the max1540 is available in a 32-pin thin qfn package with optional inductor-saturation protection and over- voltage/undervoltage protection. the max1541 is avail- able in a 40-pin thin qfn package with optional inductor-saturation protection and overvoltage/under- voltage protection. +5v bias supply (v cc and v dd ) the max1540/max1541 require a 5v bias supply in addition to the battery. this 5v bias supply is either the max1540/max1541s internal linear regulator or the notebook s 95%-efficient 5v system supply. keeping the bias supply external to the ic can improve efficiency and allows the fixed 5v or adjustable linear regulator (max1541) to be used for other applications. for the max1540, the gate-driver input supply (v dd ) is connect- ed internally to the fixed 5v linear-regulator output (ldoout). dual step-down controllers with saturation protection, dynamic output, and linear regulator 22 ______________________________________________________________________________________ table 2. component suppliers supplier phone website central semiconductor 631-435-1110 (usa) www.centralsemi.com coilcraft 800-322-2645 (usa) www.coilcraft.com fairchild semiconductor 888-522-5372 (usa) www.fairchildsemi.com international rectifier 310-322-3331 (usa) www.irf.com kemet 408-986-0424 (usa) www.kemet.com panasonic 65-6231-3226 (singapore), 408-749-9714 (usa) www.panasonic.com sanyo 619-661-6835 (usa) www.sanyovideo.com siliconix (vishay) 203-268-6261 (usa) www.vishay.com sumida 408-982-9660 (usa) www.sumida.com taiyo yuden 03-3667-3408 (japan), 408-573-4150 (usa) www.t-yuden.com tdk 847-803-6100 (usa), 81-3-5201-7241 (japan) www.component.tdk.com toko 858-675-8013 (usa) www.tokoam.com
the 5v bias supply must provide v cc (pwm controller) and v dd (gate-drive power), so the maximum current drawn is: i bias = i cc + f sw (q g(low) + q g(high) ) = 4ma to 50ma (typ) where i cc is 1.1ma (typ), f sw is the switching frequency, and q g(low) and q g(high) are the mosfet data sheet s total gate-charge specification limits at v gs = 5v. the v+ battery input and 5v bias inputs (v cc and v dd ) can be connected together if the input source is a fixed 4.5v to 5.5v supply. if the 5v bias supply powers up prior to the battery supply, the enable signals (on1 and on2 going from low to high) must be delayed until the battery voltage is present in order to ensure startup. free-running, constant on-time, pwm controller with input feed forward the quick-pwm control architecture is a pseudofixed- frequency, constant on-time, current-mode regulator with voltage feed forward (figure 2). this architecture relies on the output filter capacitor s esr to act as a current-sense resistor, so the output ripple voltage pro- vides the pwm ramp signal. the quick-pwm algorithm is simple: the high-side switch on-time relies solely on an adjustable one-shot whose pulse width is inversely proportional to input voltage and directly proportional to output voltage. another one-shot sets a fixed minimum off-time (400ns typ). the controller triggers the on-time one-shot when the error comparator is low, the inductor current is below the valley current-limit threshold, and the minimum off-time one-shot has timed out. on-time one-shot (ton) the heart of the pwm core is the one-shot that sets the high-side switch on-time. this fast, low-jitter, adjustable one-shot includes circuitry that varies the on-time in response to the battery and output voltages. the high- side switch on-time is inversely proportional to the bat- tery voltage as measured by the v+ input (v in = v+), and proportional to the output voltage as measured by the out_ input: where k (switching period) is set by the ton pin-strap connection (table 3). this algorithm results in a nearly constant switching frequency despite the lack of a fixed- frequency clock generator. the benefits of a constant switching frequency are twofold: 1) the frequency can be selected to avoid noise-sensitive regions such as the 455khz if band and 2) the inductor ripple-current oper- ating point remains relatively constant, resulting in easy design methodology and predictable output voltage rip- ple. the on-time for the main controller (dh1) is set 15% higher than the nominal frequency setting (200khz, 300khz, 420khz, or 540khz), while the on-time for the secondary controller (dh2) is set 15% lower than the nominal setting. this prevents audio-frequency beat- ing between the two asynchronous regulators. the on-time one-shot has good accuracy at the operat- ing points specified in the electrical characteristics (approximately 12.5% at 540khz and 420khz nominal settings, and 10% with the 300khz and 200khz set- tings). on-times at operating points far removed from the conditions specified in the electrical characteristics can vary over a wider range. the constant on-time translates only roughly to a constant switching frequency. the on-times guaranteed in the electrical characteristics are influenced by resistive loss- es and by switching delays in the high-side mosfet. resistive losses including the inductor, both mosfets, and pc board copper losses in the output and ground tend to raise the switching frequency as the load increas- es. the dead-time effect increases the effective on-time, reducing the switching frequency as one or both dead times add to the effective on-time. it occurs only in pwm mode ( skip = v cc ) and during dynamic output-voltage transitions when the inductor current reverses at light- or negative-load currents. with reversed inductor current, the inductor s emf causes lx_ to go high earlier than normal, extending the on-time by a period equal to the driver dead time. for loads above the critical conduction point, where the dead-time effect no longer occurs, the actual switching frequency is: where v drop1 is the sum of the parasitic voltage drops in the inductor discharge path, including synchronous rectifier, inductor, and pc board resistances; v drop2 is the sum of the resistances in the charging path, includ- ing the high-side switch, inductor, and pc board resis- tances; and t on is the on-time calculated by the max1540/max1541. f sw out_ drop1 on in drop1 drop2 v+v tv+v -v = () on- time v v out in = ? ? ? ? ? ? k max1540/max1541 dual step-down controllers with saturation protection, dynamic output, and linear regulator ______________________________________________________________________________________ 23
max1540/max1541 dual step-down controllers with saturation protection, dynamic output, and linear regulator 24 ______________________________________________________________________________________ figure 2. max1540/max1541 functional diagram valley current limit zero crossing saturation limit valley current limit zero crossing saturation limit *v+ ton skip ilim1 csp1 csn1 bst1 dh1 lx1 *v dd dl1 **cc1 gnd lsat ilim2 csp2 csn2 bst2 dh2 lx2 *v dd v cc dl2 gnd ref 13r 0.7v 7r current limit 1 (figure 5) current limit 2 (figure 5) pwm controller 1 (figure 3) pwm controller 2 (figure 3) fb1 decode (figure 10) power-good and fault protection 1 (figure 9) fb2 decode (figure 10) internal max1540/max1541 option power-good and fault protection 2 (figure 9) fb1 **refin1 out1 on1 pgood1 fb2 out2 2.0v ref on2 pgood2 fault1 int ref1 int fb1 int fb2 fault2 quad-level decode quad-level decode and timer **fblank **od ovp/uvp blank enable ovp enable uvp linear regulator (figure 13) *ldoin *ldoout **fbldo ldoon **gate max1541 controller 1 only max1540/max1541 int ref2 *for the max1540: ldoin is connected to v+. ldoout is connected to v dd . **max1541 controller only.
light-load operation ( s s k k i i p p ) the four-level skip input selects light-load, pulse-skip- ping operation by independently enabling or disabling the zero-crossing comparator for each controller (table 4). when the zero-crossing comparator is enabled, the controller forces dl_ low when the current-sense inputs detect zero inductor current. this keeps the inductor from discharging the output capacitors and forces the controller to skip pulses under light-load conditions to avoid overcharging the output. when the zero-crossing comparator is disabled, the controller maintains pwm operation under light-load conditions (see the forced- pwm mode section). automatic pulse-skipping mode in skip mode, an inherent automatic switchover to pfm takes place at light loads (figure 3). this switchover is affected by a comparator that truncates the low-side switch on-time at the inductor current s zero crossing. the zero-crossing comparator differentially senses the inductor current across the current-sense inputs (csp_ to csn_). once v csp_ - v csn_ drops below 5% of the current-limit threshold (2.5mv for the default 50mv cur- rent-limit threshold), the comparator forces dl_ low (figure 3). this mechanism causes the threshold between pulse-skipping pfm and nonskipping pwm operation to coincide with the boundary between con- tinuous and discontinuous inductor-current operation (also known as the critical-conduction point). the load-current level at which pfm/pwm crossover occurs, i load(skip) , is equal to half the peak-to-peak ripple current, which is a function of the inductor value (figure 4). this threshold is relatively constant, with only a minor dependence on battery voltage: where k is the on-time scale factor (table 3). for exam- ple, in the max1541 standard application circuit (figure 12) (k = 3.0s, v out2 = 2.5v, v in = 12v, and l = 4.3h), the pulse-skipping switchover occurs at: the crossover point occurs at an even lower value if a swinging (soft-saturation) inductor is used. the switch- ing waveforms may appear noisy and asynchronous when light loading causes pulse-skipping operation, but this is a normal operating condition that results in high light-load efficiency. trade-offs in pfm noise vs. light-load efficiency are made by varying the inductor value. generally, low inductor values produce a broad- er efficiency vs. load curve, while higher values result in higher full-load efficiency (assuming that the coil resis- tance remains fixed) and less output voltage ripple. penalties for using higher inductor values include larger physical size and degraded load-transient response (especially at low input-voltage levels). dc-output accuracy specifications refer to the thresh- old of the error comparator. when the inductor is in continuous conduction, the max1540/max1541 regu- late the valley of the output ripple, so the actual dc out- put voltage is higher than the trip level by 50% of the output ripple voltage. in discontinuous conduction (i out < i load(skip) ), the output voltage has a dc regu- lation level higher than the error-comparator threshold by approximately 1.5% due to slope compensation. . . 2.5v 3 s 2 4.3 h 12v - 2.5v 12v ? ? ? ? ? ? ? ? ? ? ? ? = 0 069 a i load(skip) out in out in vk 2l v-v v ? ? ? ? ? ? ? ? ? ? ? ? max1540/max1541 dual step-down controllers with saturation protection, dynamic output, and linear regulator ______________________________________________________________________________________ 25 table 3. approximate k-factor errors controller 1 (out1) controller 2 (out2) nominal ton setting (khz) k-factor error (%) typical k-factor (s) minimum v in at v out1 = 1.8v* (v) typical k-factor (s) minimum v in at v out2 = 2.5v* (v) 200khz (ton = v cc ) 10 4.5 (235khz) 2.28 6.2 (170khz) 2.96 300khz (ton = open) 10 3.0 (345khz) 2.52 4.1 (255khz) 3.18 420khz (ton = ref) 12.5 2.2 (485khz) 2.91 3.0 (355khz) 3.48 540khz (ton = gnd) 12.5 1.7 (620khz) 3.42 2.3 (460khz) 3.87 * see the step-down converter dropout performance section (h = 1.5 and worst-case k-factor value used). table 4. skip configuration table skip out1 mode out2 mode v cc forced pwm forced pwm open forced pwm pulse skipping ref pulse skipping forced pwm gnd pulse skipping pulse skipping
max1540/max1541 forced-pwm mode the low-noise forced-pwm mode disables the zero- crossing comparator, which controls the low-side switch on-time. this forces the low-side gate-drive waveform to be constantly the complement of the high- side gate-drive waveform, so the inductor current reverses at light loads while dh_ maintains a duty fac- tor of v out_ / v in . the benefit of forced-pwm mode is to keep the switching frequency fairly constant. however, forced-pwm operation comes at a cost: the no-load 5v bias current remains between 4ma to 40ma, depending on the external mosfets and switching frequency. forced-pwm mode is most useful for reducing audio- frequency noise, improving load-transient response, and providing sink-current capability for dynamic out- put-voltage adjustment. the max1541 uses forced- pwm operation during all dynamic output-voltage transitions (gate transition detected) in order to ensure fast, accurate transitions. since forced-pwm operation disables the zero-crossing comparator, the inductor current reverses under light loads, quickly discharging the output capacitors. fblank determines how long the max1541 maintains forced-pwm operation typi- cally 220s (fblank = v cc ), 140s (fblank = open or gnd), or 65s (fblank = ref). current-limit protection (ilim_) valley current limit the current-limit circuit employs a unique valley cur- rent-sensing algorithm that uses a current-sense resistor between csp_ and csn_ as the current-sensing ele- ment (figure 1). if the magnitude of the current-sense signal is above the valley current-limit threshold, the pwm controller is not allowed to initiate a new cycle dual step-down controllers with saturation protection, dynamic output, and linear regulator 26 ______________________________________________________________________________________ figure 3. max1540/max1541 pwm-controller functional diagram valley current limit on-time compute v+ ton error amp saturation limit s r q s r q dh driver 1-shot trig q t off(min) 1-shot trig q t on out_ zero crossing fault protection dl driver int ref_ int fb_ slope comp cc1 *main max1541 controller (out1) only cc1 7r r g m = 80 a v figure 4. pulse-skipping/discontinuous crossover point inductor current i load = i peak /2 on-time 0 time i peak l v in - v out ? i ? t =
(figures 3 and 5). the actual peak current is greater than the valley current-limit threshold by an amount equal to the inductor ripple current. therefore, the exact current-limit characteristic and maximum load capability are a function of the current-sense resistance, inductor value, and battery voltage. when combined with the undervoltage protection circuit, this current-limit method is effective in almost every circumstance. figure 6 shows the valley current-limit threshold point. in forced-pwm mode, the max1540/max1541 also implement a negative current limit to prevent excessive reverse inductor currents when v out is sinking current. the negative current-limit threshold is set to approxi- mately 120% of the positive current limit and tracks the positive current limit when ilim is adjusted. the current-limit threshold is adjusted with an external resistor-divider at ilim_. a 2a to 20a divider current is recommended for accuracy and noise immunity. the current-limit threshold adjustment range is from 25mv to 200mv. in the adjustable mode, the current-limit threshold voltage is precisely 1/10th the voltage seen at ilim_. the threshold defaults to 50mv when ilim_ is connected to v cc . the logic threshold for switchover to the 50mv default value is approximately v cc - 1v. carefully observe the pc board layout guidelines to ensure that noise and dc errors do not corrupt the dif- ferential current-sense signals seen by csp_ and csn_. place the ic close to the sense resistor with short, direct traces, making a kelvin-sense connection to the current-sense resistor. max1540/max1541 dual step-down controllers with saturation protection, dynamic output, and linear regulator ______________________________________________________________________________________ 27 figure 5. max1540/max1541 current-limit functional diagram s r q quad-level decode saturation limit valley current limit zero crossing dh driver 9r r 0.5v csp_ skip csn_ ilim_ 6 a v cc - 1.0v lsat figure 6. valley current-limit threshold point inductor current i limit i load 0 time i peak i lim(val) = i load(max) 1- lir 2 ()
max1540/max1541 inductor-saturation limit the lsat connection selects an upper current-sense limit as the inductor-saturation threshold, or disables the inductor-saturation protection feature altogether (lsat = gnd). when enabled, the inductor-saturation threshold is a multiple of the positive valley current-limit threshold (table 5) and tracks the valley current limit when ilim is adjusted. the selected inductor-saturation threshold should give sufficient headroom above the peak inductor current so switching noise does not acci- dentally trip the saturation protection. selecting an excessively high threshold may allow inductor satura- tion to go undetected. for an inductor with a low lir (the ratio of the inductor ripple current to the designed maximum load current) near 20%, select the lowest sat- uration threshold of 1.5 x i lim(val) (lsat = ref). when using an inductor with a higher lir, increase the induc- tor-saturation threshold accordingly. when inductor-saturation protection is enabled, the max1540/max1541 continuously monitor the inductor current through the voltage across the current-sense resistor. when the inductor-saturation threshold is exceeded, the max1540/max1541 immediately turn off the high-side gate driver and enable a 6a discharge current on ilim_ (figure 7) at the beginning of the next dh_ on-time. this reduces the voltage on ilim_ by ? v ilim where: where the ilim saturation fault sink current (i ilim(lsat) ) is typically 6a (see the electrical characteristics table). when using the default 50mv valley current-limit threshold (ilim_ = v cc ), the ilim_ saturation fault sink current does not lower the current-limit threshold (figure 5). if the inductor current remains below the saturation threshold during the next cycle, the controller disables the ilim_ discharge current, allowing the ilim_ voltage to return to its nominal set point. the inductor should not remain in saturation once the controller reduces the valley current limit. if the inductor remains saturated, the output voltage may drop low enough to trip the undervoltage fault protection (uvp enabled), causing the max1540/max1541 to set the fault latch and shut down both outputs. adding a capacitor from ilim_ to gnd slows the ilim_ voltage change by the time con- stant = (r a //r b ) x c ilim , where is between 5 to 10 switching periods. if the inductor saturation occurs only during a short load transient, the time constant allows the power supply to recover before the output voltage drops below the output undervoltage threshold. set ? v ilim to be at least 30% of the ilim_ set voltage. calculate r a and r b using the equations below: inductor-saturation sensing works best when using a cur- rent-sense resistor in series with the inductor. see the setting the current limit section for various current-sense configurations (figure 14) and lsat recommendations. r with set at r a ref ilim(lsat) ilim ilim(set) ilim ilim(set) b a ref ilim(set) v i v v v v r v v - = ? ? ? ? ? ? ? ? ? ? ? ? = ? ? ? ? ? ? ?? 30 1 % ? vi ilim ab ab ilim(lsat) - rr r+r = ? ? ? ? ? ? dual step-down controllers with saturation protection, dynamic output, and linear regulator 28 ______________________________________________________________________________________ max1540 max1541 ref ilim 6 a c ref to valley current-limit comparator (figure 2) from lsat comparator and logic (figure 2) c ilim r b r a figure 7. adjustable current-limit threshold table 5. lsat configuration table lsat inductor-saturation threshold v cc 2.00 x i lim(val) open 1.75 x i lim(val) ref 1.50 x i lim(val) gnd disabled
mosfet gate drivers (dh_, dl_) the dh_ and dl_ drivers are optimized for driving mod- erate-sized high-side, and larger low-side power mosfets. this is consistent with the low duty factor seen in notebook applications where a large v in - v out differential exists. an adaptive dead-time circuit moni- tors the dl_ output and prevents the high-side mosfet from turning on until dl_ is off. a similar adaptive dead- time circuit monitors the dh_ output, preventing the low- side mosfet from turning on until dh_ is off. there must be a low-resistance, low-inductance path from the dl_ and dh_ drivers to the mosfet gates for the adap- tive dead-time circuits to work properly; otherwise, the sense circuitry in the max1540/max1541 interprets the mosfet gates as off while charge actually remains. use very short, wide traces (50 mils to 100 mils wide if the mosfet is 1in from the driver). the internal pulldown transistor that drives dl_ low is robust, with a 0.6 ? (typ) on-resistance. this helps pre- vent dl_ from being pulled up due to capacitive cou- pling from the drain to the gate of the low-side mosfets when the inductor node (lx_) quickly switches from ground to v in . applications with high input voltages and long inductive driver traces may require additional gate- to-source capacitance to ensure fast-rising lx_ edges do not pull up the low-side mosfets gate, causing shoot-through currents. the capacitive coupling between lx_ and dl_ created by the mosfet s gate-to- drain capacitance (c rss ), gate-to-source capacitance (c iss -c rss ), and additional board parasitics should not exceed the following minimum threshold: lot-to-lot variation of the threshold voltage can cause problems in marginal designs. alternatively, adding a resistor less than 10 ? in series with bst_ can remedy the problem by increasing the turn-on time of the high-side mosfet without degrading the turn-off time (figure 8). por, uvlo, and soft-start power-on reset (por) occurs when v cc rises above approximately 2v, resetting the fault latch and soft-start counter, powering-up the reference, and preparing the pwm for operation. until v cc reaches 4.25v (typ), v cc undervoltage lockout (uvlo) circuitry inhibits switching. the controller inhibits switching by pulling dh_ low, and holding dl_ low when ovp and shutdown discharge are disabled or forcing dl_ high when ovp and shutdown discharge are enabled (table 7). when v cc rises above 4.25v and on_ is driven high, the controller activates the pwm controller and initializes soft-start. soft-start allows a gradual increase of the internal current- limit level during startup to reduce the input surge cur- rents. the max1540/max1541 divide the soft-start period into five phases. during the first phase, the controller lim- its the current limit to only 20% of the full current limit. if the output does not reach regulation within 425s, soft- start enters the second phase, and the current limit is increased by another 20%. this process is repeated until the maximum current limit is reached after 1.7ms or when the output reaches the nominal regulation voltage, whichever occurs first (see the soft-start waveforms in the typical operating characteristics ). power-good output (pgood_) pgood_ is the open-drain output for a window com- parator that continuously monitors the output. pgood_ is actively held low in shutdown and during soft-start. after the digital soft-start terminates, pgood_ becomes high impedance as long as the respective output volt- age is within 10% of the nominal regulation voltage set by fb_. when the output voltage drops 10% below or rises 10% above the nominal regulation voltage, the max1540/max1541 pull the respective power-good out- put (pgood_) low by turning on the mosfet (figure 9). any fault condition forces both pgood1 and pgood2 low until the fault latch is cleared by toggling vv gs(th) in rss iss c c < ? ? ? ? ? ? max1540/max1541 dual step-down controllers with saturation protection, dynamic output, and linear regulator ______________________________________________________________________________________________________ 29 figure 8. optional gate-driver circuitry max1540 max1541 v dd bst dh lx (r bst )* (c nl )* d bst c bst c byp input (v in ) n h l v dd dl pgnd n l (r bst )* optional?he resistor lowers emi by decreasing the switching node rise time. (c nl )* optional?he capacitor reduces lx to dl capacitive coupling that can cause shoot-through currents.
max1540/max1541 on1 or on2, or cycling v cc power below 1v. for logic- level output voltages, connect an external pullup resis- tor between pgood_ and v cc . a 100k ? resistor works well in most applications. note that the power-good window detectors are com- pletely independent of the overvoltage and undervolt- age-protection fault detectors. fault blanking (max1541 fblank) the main max1541 controller (out1) automatically enters forced-pwm operation during all dynamic output- voltage transitions (gate transition detected) in order to ensure fast, accurate transitions. fblank determines how long the main max1541 controller maintains forced- pwm operation (table 6 typically 220s (fblank = v cc ), 140s (fblank = open or gnd), or 65s (fblank = ref). when fault blanking is enabled (fblank = v cc , open, or ref), the max1541 also disables the overvoltage and undervoltage fault protection for out1, and forces pgood1 to a high-impedance state during the transi- tion period selected by fblank (table 6). this pre- vents fault protection from latching off the max1541 and the pgood1 signal from going low when the out- put voltage change ( ? v out1 ) cannot occur as fast as the refin1 voltage change ( ? v refin1 ). shutdown and output discharge (on_) when the output discharge mode is enabled (ovp/uvp connected to v cc or left open), and either on_ is pulled low or an ovp fault or thermal fault sets the fault latch (table 7), the controller discharges each output through an internal 10 ? switch connected between out_ and ground. while the output discharges, dl_ is forced low and the pwm controller is disabled. once the output voltage drops below 0.3v, the low-side driver pulls dl_ high, effectively clamping the output and lx_ switching node to ground. the reference remains active until both output voltages are below 0.3v to provide an accurate 0.3v discharge threshold. when ovp/uvp is connected to ref or gnd, the con- troller does not actively discharge either output, and the dl_ driver remains low until the system reenables the controller. under these conditions, the output discharge rate is determined by the load current and output capacitance. the controller detects and latches the discharge-mode state set by ovp/uvp on startup. fault protection the max1540/max1541 provide over/undervoltage fault protection (figure 9). drive ovp/uvp to enable and disable fault protection as shown in table 7. once activated, the controller continuously monitors the out- put for undervoltage and overvoltage fault conditions. overvoltage protection (ovp) when the output voltage rises above 116% of the nomi- nal regulation voltage and ovp is enabled (ovp/uvp = v cc or open), the ovp circuit sets the fault latch, shuts down both the quick-pwm controllers, immediately pulls dh1 and dh2 low, and forces dl1 and dl2 high. this turns on the synchronous-rectifier mosfets with 100% duty, rapidly discharging the output capacitors and clamping both outputs to ground. note that imme- diately latching dl_ high can cause the output voltages to go slightly negative due to energy stored in the out- put lc at the instant the ov fault occurs. if the load dual step-down controllers with saturation protection, dynamic output, and linear regulator 30 ______________________________________________________________________________________ figure 9. power-good and fault protection 20ms timer fault latch por 0.9 x int ref_ 1.1 x int ref_ 0.7 x int ref_ 1.14 x int ref_ int fb_ enable ovp enable uvp *blank fault power- good *main max1541 controller (out1) only power-good fault protection table 6. fblank configuration table fblank out1 fault blanking forced-pwm duration (min/typ) (s) v cc enabled 120/220 open enabled 80/140 ref enabled 35/65 gnd disabled 80/140
cannot tolerate a negative voltage, place a power schottky diode across the output to act as a reverse- polarity clamp. if the condition that caused the overvolt- age persists (such as a shorted high-side mosfet), the input fuse blows. the max1541 ignores ovp faults on out1 when it detects a transition on gate (fblank enabled). toggle on1 or on2, or cycle v cc power below 1v to clear the fault latch and restart the controller. ovp is disabled when ovp/uvp is connected to ref or gnd (table 7). undervoltage protection (uvp) when the output voltage drops below 70% of the nomi- nal regulation voltage and uvp is enabled (ovp/uvp = v cc or ref), the controller sets the fault latch and acti- vates the output discharge sequence (see the shutdown and output discharge section) of both out- puts. when the output voltage drops to 0.3v, the driver pulls dl high so the synchronous rectifier turns on, clamping the output to gnd. uvp is ignored for at least 10ms (min) after startup (on_ rising edge), and when transitions are detected on gate (max1541 only, fblank enabled). toggle on1 or on2, or cycle v cc power below 1v to clear the fault latch and restart the controller. uvp is disabled when ovp/uvp is left open or connect- ed to gnd (table 7). thermal fault protection the max1540/max1541 feature a thermal fault-protec- tion circuit. when the linear regulator is disabled (ldoon = gnd), the controller sets the thermal limit at +160 c. when the linear regulator is enabled (ldoon = v cc ), the controller sets the thermal limit at +150 c to protect the internal linear regulator from continuous short-circuit conditions. once the junction temperature exceeds the thermal limit, the thermal-protection circuit activates the fault latch, pulls pgood1 and pgood2 low, disables the linear regulator, and activates the out- put discharge sequence of both outputs regardless of the ovp/uvp setting. toggle on1 or on2, or cycle v cc power below 1v to reactivate the controller after the junction temperature cools by 10 c. output voltage preset output voltages the max1540/max1541s dual mode operation allows the selection of common voltages without requiring external components (figure 10). for the main con- troller (out1) of the max1540, connect fb1 to gnd for a fixed 1.8v output, to v cc for a fixed 1.2v output, or connect fb1 directly to out1 for a fixed 0.7v output. for the secondary controller (out2) of the max1540, connect fb2 to gnd for a fixed 2.5v output, to v cc for a fixed 1.5v output, or connect fb2 directly to out2 for a fixed 0.7v output. the main controller (out1) of the max1541 regulates to the voltage set at refin1 (v fb1 = v refin1 ) and does not support dual mode operation. for the secondary controller (out2) of the max1541, connect fb2 to gnd for a fixed 2.5v output, to v cc for a fixed 1.8v output, or connect fb2 directly to out2 for a fixed 0.7v output. table 8 shows the output voltage configuration. max1540/max1541 dual step-down controllers with saturation protection, dynamic output, and linear regulator ______________________________________________________________________________________ 31 table 7. fault protection and shutdown setting truth table ovp/uvp on_ discharge* uvp protection ovp protection thermal protection v cc yes. output discharged through a 10 ? resistor, and dl forced high when output drops below 0.3v. yes. uvp fault activates the discharge sequence. yes. dh pulled low and dl forced high immediately. yes. thermal fault activates the discharge sequence. open yes. output discharged through a 10 ? resistor, and dl forced high when output drops below 0.3v. no. uvp disabled. yes. dh pulled low and dl forced high immediately. yes. thermal fault activates the discharge sequence. ref no. dl forced low when shut down. yes. uvp fault activates the discharge sequence. no. ovp disabled. yes. thermal fault activates the discharge sequence. gnd no. dl forced low when shut down. no. uvp disabled. no. ovp disabled. yes. thermal fault activates the discharge sequence. * discharge-mode state latched on power-up.
max1540/max1541 setting v out with a resistive voltage-divider at fb_ the output voltage can be adjusted from 0.7v to 5.5v using a resistive voltage-divider (figure 11). the max1540 regulates fb1 and fb2 to a fixed 0.7v refer- ence voltage. the max1541 regulates fb1 to the volt- age set at refin1 and regulates fb2 to a fixed 0.7v reference voltage. this makes the main max1541 con- troller (out1) ideal for memory applications where the termination supply must track the supply voltage. the adjusted output voltage is: where v fb_ = 0.7v for the max1540, and v fb1 = v refin1 and v fb2 = 0.7v for the max1541. dynamic output voltages (max1541 out1 only) the max1541 regulates fb1 to the voltage set at refin1. by changing the voltage at refin1, the max1541 can be used in applications that require dynamic output-voltage changes between two set points. figure 12 shows a dynamically adjustable resis- tive voltage-divider network at refin1. using the gate signal and open-drain output (od), a resistor can be switched in and out of the refin1 resistor-divider, changing the voltage at refin1. a logic high on gate turns on the internal n-channel mosfet, forcing od to a low-impedance state. a logic low on gate disables the n-channel mosfet, so od is high impedance. the two output voltages (fb1 = out1) are determined by the following equations: the main max1541 controller (out1) automatically enters forced-pwm operation on the rising and falling edges of gate, and remains in forced-pwm mode for a minimum time selected by fblank (table 6). forced- pwm operation is required to ensure fast, accurate negative voltage transitions when refin1 is lowered. since forced-pwm operation disables the zero-crossing comparator, the inductor current may reverse under vv vv out1(low) ref out1(high) ref r9 r8+r9 (r9+r10) r8+(r9+r10) = ? ? ? ? ? ? = ? ? ? ? ? ? vv out_ fb_ c d r r =+ ? ? ? ? ? ? 1 dual step-down controllers with saturation protection, dynamic output, and linear regulator 32 ______________________________________________________________________________________ figure 10. max1540/max1541 dual mode feedback decoder max1540 max1541 to error amplifier fb_ ref (2.0v) fixed output fb = gnd fixed output fb = v cc out_ 9r r table 8. output voltage configuration out1 out2 max1540 max1541 max1540 max1541 fb_ = v cc fixed 1.2v not allowed fixed 1.5v fixed 1.8v fb_ = gnd fixed 1.8v not allowed fixed 2.5v fixed 2.5v fb_ = out_ or adjustable 0.7v v refin1 0.7v 0.7v
light loads, quickly discharging the output capacitors. if fault blanking is enabled, the max1541 also disables the main controller s (out1) overvoltage and undervolt- age fault protection, and forces pgood1 to a high- impedance state for the period selected by fblank (table 6). for a step-voltage change at refin1, the rate of change of the output voltage is limited by the inductor current ramp, the total output capacitance, the current limit, and the load during the transition. the inductor current ramp is limited by the voltage across the induc- tor and the inductance. the total output capacitance determines how much current is needed to change the output voltage. additional load current slows down the output-voltage change during a positive refin1 volt- age change, and speeds up the output-voltage change during a negative refin1 voltage change. for fast pos- itive output-voltage transitions, the current limit must be greater than the load current plus the transition current: adding a capacitor across refin1 and gnd filters noise and controls the rate of change of the refin1 voltage during dynamic transitions. with the additional capacitance, the refin1 voltage slews between the two set points with a time constant given by r eq x c refin1 , where r eq is the equivalent parallel resis- tance seen by the slew capacitor. looking at figure 12, the time constant for a positive refin1 voltage transi- tion is: and the time constant for a negative refin1 voltage transition is: linear regulator (ldo) the maximum input voltage for the linear regulator is 28v, while the minimum input voltage is determined by the 600mv (max) dropout voltage (v ldoin(min) = v ldoout + v dropout ). bypass the linear regulator s output (ldoout) with a 4.7f or greater capacitor, providing at least 1f per 5ma of internal and external load on the linear regulator. the ldo can source up to 100ma for powering the controller or supplying a small external load. for the max1540, the linear regulator provides the 5v bias supply that powers the gate drivers and analog controller (figure 1), providing stand-alone capability. the linear regulator s input is internally connected to the battery voltage input (ldoin = v+), and the gate- driver input supply is internally connected to the linear regulator s output (v dd = ldoout). figure 13 is the internal linear-regulator functional diagram. for the max1541, the linear regulator supports dual mode operation to allow the selection of a 5v output voltage without requiring external components (figure 1). connect fbldo to gnd for a fixed 5.0v output. the linear regulator s output voltage can be adjusted from 1.25v to 5.5v using a resistive voltage-divider (figure 12). the max1541 regulates fbldo to a 1.25v feed- back voltage. the adjusted output voltage is: where v fbldo = 1.25v. if unused, disable the max1541 linear regulator by connecting ldoon to gnd. vv r r ldoout fbldo =+ ? ? ? ? ? ? 1 11 12 neg refin1 r8 r9 r8+r9 = ? ? ? ? ? ? c pos = refin1 r8 (r9+r10) r8+(r9+r10) ? ? ? ? ? ? c ii c d d oad out v t limit l >+ max1540/max1541 dual step-down controllers with saturation protection, dynamic output, and linear regulator ______________________________________________________________________________________ 33 figure 11. setting v out with a resistive voltage-divider at fb_ max1540 max1541 dl_ gnd lx_ l fb_ csn_ csp_ r d r c c out r sense n l out_
max1540/max1541 dual step-down controllers with saturation protection, dynamic output, and linear regulator 34 ______________________________________________________________________________________ figure 12. max1541 standard application circuit max1541 +5v bias supply output 1 v out(high) = 1.5v v out(low) = 1.0v power ground analog ground power-good on off open (i lim(val) x 1.75) output 2 v out2 = 2.5v input (v in )* 7v to 20v v dd dh1 bst1 lx1 csp1 dl1 csn1 out1 fb1 cc1 skip ref ilim1 ilim2 pgood2 ldoin pgood1 v cc on2 on1 ldoon lsat ref (485khz/355khz) ton ovp/uvp fb2 out2 csn2 csp2 gnd dl2 lx2 bst2 dh2 v+ r7 100k ? r6 100k ? c2 1 f c3 4.7 f r1 20 ? c out2 220 f r cs2 15m ? l2 4.3 h d l2 d l1 r cs1 15m ? l1 1.8 h n l1 n l2 n h1 n h2 c bst 0.1 f c bst1 0.1 f d bst d bst c1 1 f c ref 0.22 f c out1 470 f c ilim1 470pf c ilim2 470pf r2 100k ? r3 49.9k ? r4 100k ? r5 49.9k ? see table 1 for component specifications. *lower input voltages require additional input capacitance. c cc1 47pf v out(low) v out(high) gate fblank refin1 od open (enabled, 140 s) ref r9 75k ? r10 150k ? r8 75k ? c refin 470pf r12 20k ? +5v bias supply c in (2) 4.7 f v out(low) = v ref v out(high) = v ref r9 r8 + r9 () (r9 + r10) r8 + (r9 + r10) [] ldoout fbldo +5v bias supply r13 10 ? r11 32.4k ? c4 22 f ldo output v ldoout = 3.3v ()
design procedure firmly establish the input voltage range and maximum load current before choosing a switching frequency and inductor operating point (ripple-current ratio). the primary design trade-off lies in choosing a good switch- ing frequency and inductor operating point, and the fol- lowing four factors dictate the rest of the design: input voltage range: the maximum value (v in(max) ) must accommodate the worst-case, high ac-adapter voltage. the minimum value (v in(min) ) must account for the lowest battery voltage after drops due to con- nectors, fuses, and battery selector switches. if there is a choice at all, lower input voltages result in better efficiency. maximum load current: there are two values to consider. the peak load current (i load(max) ) deter- mines the instantaneous component stresses and fil- tering requirements and thus drives output capacitor selection, inductor saturation rating, and the design of the current-limit circuit. the continuous load current (i load ) determines the thermal stresses and thus dri- ves the selection of input capacitors, mosfets, and other critical heat-contributing components. switching frequency: this choice determines the basic trade-off between size and efficiency. the optimal frequency is largely a function of maximum input voltage due to mosfet switching losses that are proportional to frequency and v in2 . the opti- mum frequency is also a moving target, due to rapid improvements in mosfet technology that are making higher frequencies more practical. inductor operating point: this choice provides trade-offs between size vs. efficiency and transient response vs. output ripple. low inductor values provide better transient response and smaller phys- ical size, but also result in lower efficiency and higher output ripple due to increased ripple cur- rents. the minimum practical inductor value is one that causes the circuit to operate at the edge of crit- ical conduction (where the inductor current just touches zero with every cycle at maximum load). inductor values lower than this grant no further size- reduction benefit. the optimum operating point is usually found between 20% and 50% ripple current. when pulse skipping ( skip low and light loads), the inductor value also determines the load-current value at which pfm/pwm switchover occurs. max1540/max1541 dual step-down controllers with saturation protection, dynamic output, and linear regulator ______________________________________________________________________________________ 35 figure 13. internal linear-regulator functional diagram vl reg and ref gate driver and error amp ldoout *v dd *max1541 only. *fbdlo ldoon *ldoin v+ 0.2v fixed 5v internal fbldo option between the max1540/max1541 internal ldoin option between the max1540/max1541 internal v dd option between the max1540/max1541
max1540/max1541 inductor selection the switching frequency and inductor operating point determine the inductor value as follows: for example: i load(max) = 4a, v in = 12v, v out2 = 2.5v, f sw = 355khz, 30% ripple current or lir = 0.3: find a low-loss inductor with the lowest possible dc resistance that fits in the allotted dimensions. ferrite cores are often the best choice, although powdered iron is inexpensive and can work well at 200khz. the core must be large enough not to saturate at the peak inductor current (i peak ): most inductor manufacturers provide inductors in stan- dard values, such as 1.0h, 1.5h, 2.2h, 3.3h, etc. also look for nonstandard values, which can provide a better compromise in lir across the input voltage range. if using a swinging inductor (where the no-load inductance decreases linearly with increasing current), evaluate the lir with properly scaled inductance values. transient response the inductor ripple current also impacts transient- response performance, especially at low v in - v out dif- ferentials. low inductor values allow the inductor current to slew faster, replenishing charge removed from the output filter capacitors by a sudden load step. the amount of output sag is also a function of the maxi- mum duty factor, which can be calculated from the on- time and minimum off-time: where t off(min) is the minimum off-time (see the electrical characteristics ) and k is from table 3. the amount of overshoot during a full-load to no-load tran- sient due to stored inductor energy can be calculated as: setting the current limit the minimum current-limit threshold must be great enough to support the maximum load current when the current limit is at the minimum tolerance value. the val- ley of the inductor current occurs at i load(max) minus half the ripple current; therefore: where i lim(val) equals the minimum valley current-limit threshold voltage divided by the current-sense resis- tance (r sense ). for the 50mv default setting, the mini- mum valley current-limit threshold is 40mv. connect ilim_ to v cc for a default 50mv valley current- limit threshold. in adjustable mode, the valley current- limit threshold is precisely 1/10th the voltage seen at ilim_. for an adjustable threshold, connect a resistive divider from ref to analog ground (gnd) with ilim_ connected to the center tap. the external 250mv to 2v adjustment range corresponds to a 25mv to 200mv valley current-limit threshold. when adjusting the current limit, use 1% tolerance resistors and a divider current of approximately 10a to prevent significant inaccuracy in the valley current-limit tolerance. the current-sense method (figure 14) and magnitude determine the achievable current-limit accuracy and power loss (table 9). typically, higher current-sense voltage limits provide tighter accuracy, but also dissi- pate more power. most applications employ a valley current-sense voltage (v lim(val) ) of 50mv to 100mv, so the sense resistor may be determined by: r sense = v lim(val) / i lim(val) for the best current-sense accuracy and overcurrent protection, use a 1% tolerance current-sense resistor between the inductor and output as shown in figure 14a. this configuration constantly monitors the inductor current, allowing accurate valley current-limiting and inductor-saturation protection. for low-output-voltage applications that require higher efficiency, the current-sense resistor can be connected between the source of the low-side mosfet (n l_ ) and power ground (figure 14b) with csn_ connected to the drain of n l_ and csp_ connected to power ground. in this configuration, the additional current-sense resis- tance only dissipates power when n l_ is conducting current. inductor-saturation protection must be dis- abled with this configuration (lsat = gnd) since the inductor current is only properly sensed when the low- side mosfet is turned on. ii vv v vfl out in min out in min sw lim(val) load(max) - - > ? ? ? ? ? ? () () () 2 v il cv soar load(max) out out 2 () ? 2 v l) vk v +t v-v k v -t sag load(max) out in off(min) out out in out in off(min) 2 = ? ? ? ? ? ? ? ? ? ? ? ? ? ? () ? ? ? ? ? ? ? ? ? ? ? ? ? ? ( ? i cv 2 ii lir peak load(max) =+ ? ? ? ? ? ? 1 2 . l khz x a = = 2.5v (12v - 2.5v) 12v 3 4 0 4.65 h 55 3 l vvv v f x i lir = () out in out in sw load(max) - dual step-down controllers with saturation protection, dynamic output, and linear regulator 36 ______________________________________________________________________________________
for high-power applications that do not require high- accuracy current sensing or inductor-saturation protec- tion, the max1540/max1541 can use the low-side mosfet s on-resistance as the current-sense element (r sense = r ds(on) ) by connecting csn_ to the drain of n l_ and csp_ to the source of n l_ (figure 14c). use the worst-case maximum value for r ds(on) from the mosfet data sheet, and add some margin for the rise in r ds(on) with temperature. a good general rule is to allow 0.5% additional resistance for each c of temper- ature rise. inductor-saturation protection must be dis- abled with this configuration (lsat = gnd) since the inductor current is only properly sensed when the low- side mosfet is turned on. alternatively, high-power applications that require inductor saturation can constantly detect the inductor current by connecting a series rc circuit across the inductor (figure 14d) with an equivalent time constant: where r l is the inductor s series dc resistance. in this configuration, the current-sense resistance is equiva- lent to the inductor s dc resistance (r sense = r l ). use the worst-case inductance and r l values provided by the inductor manufacturer, adding some margin for the inductance drop over temperature and load. in all cases, ensure an acceptable valley current-limit threshold voltage and inductor-saturation configura- tions despite inaccuracies in sense-resistance values. output capacitor selection the output filter capacitor must have low enough equiv- alent series resistance (esr) to meet output ripple and load-transient requirements, yet have high enough esr to satisfy stability requirements. for processor-core voltage converters and other appli- cations where the output is subject to violent load tran- sients, the output capacitor s size depends on how much esr is needed to prevent the output from dipping too low under a load transient. ignoring the sag due to finite capacitance: in applications without large and fast load transients, the output capacitor s size often depends on how much esr is needed to maintain an acceptable level of out- put voltage ripple. the output ripple voltage of a step- down controller equals the total inductor ripple current multiplied by the output capacitor s esr. therefore, the maximum esr required to meet ripple specifications is: the actual capacitance value required relates to the physical size needed to achieve low esr, as well as to the chemistry of the capacitor technology. thus, the capacitor is usually selected by esr and voltage rating rather than by capacitance value (this is true of tanta- lums, os-cons, polymers, and other electrolytics). when using low-capacity filter capacitors, such as ceramic capacitors, size is usually determined by the capacity needed to prevent v sag and v soar from causing problems during load transients. generally, once enough capacitance is added to meet the over- shoot requirement, undershoot at the rising load edge is no longer a problem (see the v sag and v soar equa- tions in the transient response section). however, low- capacity filter capacitors typically have high-esr zeros that may affect the overall stability (see the output- capacitor stability considerations section). r v i lir esr ripple load(max) ? r v i esr step load(max) ? l r =c r l eq eq max1540/max1541 dual step-down controllers with saturation protection, dynamic output, and linear regulator ______________________________________________________________________________________ 37 table 9. current-sense configurations method current-sense accuracy inductor-saturation protection current-sense power loss (efficiency) a) output current-sense resistor high allowed (highest accuracy) r sense x i out 2 b) low-side current-sense resistor high not allowed (lsat = gnd) c) low-side mosfet on-resistance low not allowed (lsat = gnd) no additional loss d) equivalent inductor dc resistance low allowed no additional loss 1- out in sense out 2 v v ri ? ? ? ? ? ?
max1540/max1541 dual step-down controllers with saturation protection, dynamic output, and linear regulator 38 ______________________________________________________________________________________ figure 14. current-sense configurations max1540 max1541 v out c out v in l inductor r l c in lsat d) lossless inductor sensing csn csp gnd dl dh lx disable lsat c eq r eq r bias = r eq max1540 max1541 v out c out v in l c in lsat c) low-side mosfet sensing csp gnd csn dl dh lx disable lsat max1540 max1541 v out c out v in l c in r sense lsat b) low-side series resistor sensing csp gnd csn dl dh lx connect to preferred lsat setting max1540 max1541 v out c out v in l c in lsat a) output series resistor sensing gnd dl dh lx connect to preferred lsat setting csn csp r sense
output-capacitor stability considerations for quick-pwm controllers, stability is determined by the value of the esr zero relative to the switching fre- quency. the boundary of instability is given by the fol- lowing equation: for a typical 300khz application, the esr zero frequen- cy must be well below 95khz, preferably below 50khz. tantalum and os-con capacitors in widespread use at the time of publication have typical esr zero fre- quencies of 25khz. in the design example used for inductor selection, the esr needed to support 25mv p-p ripple is 25mv/1.2a = 20.8m ? . one 220f/4v sanyo polymer (tpe) capacitor provides 15m ? (max) esr. this results in a zero at 48khz, well within the bounds of stability. do not put high-value ceramic capacitors directly across the feedback sense point without taking precau- tions to ensure stability. large ceramic capacitors can have a high-esr zero frequency and cause erratic, unstable operation. however, it is easy to add enough series resistance by placing the capacitors a couple of inches downstream from the feedback sense point, which should be as close as possible to the inductor. unstable operation manifests itself in two related but distinctly different ways: double pulsing and fast-feed- back loop instability. double pulsing occurs due to noise on the output or because the esr is so low that there is not enough voltage ramp in the output voltage signal. this fools the error comparator into triggering a new cycle immediately after the 400ns minimum off- time period has expired. double pulsing is more annoy- ing than harmful, resulting in nothing worse than increased output ripple. however, it can indicate the possible presence of loop instability due to insufficient esr. loop instability can result in oscillations at the out- put after line or load steps. such perturbations are usu- ally damped, but can cause the output voltage to rise above or fall below the tolerance limits. the easiest method for checking stability is to apply a very fast zero-to-max load transient and carefully observe the output voltage ripple envelope for over- shoot and ringing. it can help to monitor simultaneously the inductor current with an ac current probe. do not allow more than one cycle of ringing after the initial step-response under/overshoot. input-capacitor selection the input capacitor must meet the ripple current requirement (i rms ) imposed by the switching currents: for most applications, nontantalum chemistries (ceram- ic, aluminum, or os-con) are preferred due to their resistance to power-up surge currents typical of sys- tems with a mechanical switch or connector in series with the input. if the max1540/max1541 are operated as the second stage of a two-stage power conversion system, tantalum input capacitors are acceptable. in either configuration, choose a capacitor that has less than 10 c temperature rise at the rms input current for optimal reliability and lifetime. power mosfet selection most of the following mosfet guidelines focus on the challenge of obtaining high load-current capability when using high-voltage (>20v) ac adapters. low-cur- rent applications usually require less attention. the high-side mosfet (n h ) must be able to dissipate the resistive losses plus the switching losses at both v in(min) and v in(max) . ideally, the losses at v in(min) should be roughly equal to the losses at v in(max) , with lower losses in between. if the losses at v in(min) are significantly higher, consider increasing the size of n h . conversely, if the losses at v in(max) are significantly higher, consider reducing the size of n h . if v in does not vary over a wide range, maximum efficiency is achieved by selecting a high-side mosfet (n h ) that has conduction losses equal to the switching losses. choose a low-side mosfet (n l ) that has the lowest pos- sible on-resistance (r ds(on) ), comes in a moderate-sized package (i.e., 8-pin so, dpak, or d 2 pak), and is reason- ably priced. ensure that the max1540/max1541 dl_ gate driver can supply sufficient current to support the gate charge and the current injected into the parasitic drain-to-gate capacitor caused by the high-side mosfet turning on; otherwise, cross-conduction problems may occur. switching losses are not an issue for the low-side mosfet since it is a zero-voltage switched device when used in the step-down topology. i rms = ?+ ? () ( ) () ( ) ivvv ivvv v out out in out out out in out in 1 2 11 2 2 22 f f where f 1 2r c esr sw esr esr out = max1540/max1541 dual step-down controllers with saturation protection, dynamic output, and linear regulator ______________________________________________________________________________________ 39
max1540/max1541 power-mosfet dissipation worst-case conduction losses occur at the duty factor extremes. for the high-side mosfet (n h ), the worst- case power dissipation due to resistance occurs at minimum input voltage: generally, use a small high-side mosfet to reduce switching losses at high input voltages. however, the r ds(on) required to stay within package power-dissi- pation limits often restricts how small the mosfet can be. the optimum occurs when the switching losses equal the conduction (r ds(on) ) losses. high-side switching losses do not become an issue until the input is greater than approximately 15v. calculating the power dissipation in high-side mosfets (n h ) due to switching losses is difficult, since it must allow for difficult-to-quantify factors that influ- ence the turn-on and turn-off times. these factors include the internal gate resistance, gate charge, threshold voltage, source inductance, and pc board layout characteristics. the following switching loss cal- culation provides only a very rough estimate and is no substitute for breadboard evaluation, preferably includ- ing verification using a thermocouple mounted on n h : where c rss is the reverse transfer capacitance of n h , and i gate is the peak gate-drive source/sink current (1a typ). switching losses in the high-side mosfet can become a heat problem when maximum ac adapter voltages are applied due to the squared term in the switching- loss equation (c ? v in 2 ? f sw ). if the high-side mos- fet chosen for adequate r ds(on) at low-battery voltages becomes extraordinarily hot when subjected to v in(max) , consider choosing another mosfet with lower parasitic capacitance. for the low-side mosfet (n l ), the worst-case power dissipation always occurs at maximum battery voltage: the absolute worst case for mosfet power dissipation occurs under heavy overload conditions that are greater than i load(max) but are not high enough to exceed the current limit and cause the fault latch to trip. to protect against this possibility, overdesign the cir- cuit to tolerate: where i valley(max) is the maximum valley current allowed by the current-limit circuit, including threshold tolerance and sense-resistance variation. the mosfets must have a relatively large heatsink to han- dle the overload power dissipation. choose a schottky diode (d l ) with a forward-voltage drop low enough to prevent the low-side mosfet s body diode from turning on during the dead time. as a general rule, select a diode with a dc current rating equal to 1/3 the load current. this diode is optional and can be removed if efficiency is not critical. applications information step-down converter dropout performance the output-voltage adjustable range for continuous- conduction operation is restricted by the nonadjustable minimum off-time one-shot. for best dropout perfor- mance, use the slower (200khz) on-time setting. when working with low input voltages, the duty-factor limit must be calculated using worst-case values for on- and off-times. manufacturing tolerances and internal propa- gation delays introduce an error to the ton k-factor. this error is greater at higher frequencies (table 3). also, keep in mind that transient-response performance of buck regulators operated too close to dropout is poor, and bulk output capacitance must often be added (see the v sag equation in the design procedure section). the absolute point of dropout is when the inductor cur- rent ramps down during the minimum off-time ( ? i down ) as much as it ramps up during the on-time ( ? i up ). the ratio h = ? i up / ? i down indicates the controller s ability to slew the inductor current higher in response to increased load, and must always be greater than 1. as h approaches 1, the absolute minimum dropout point, the inductor current cannot increase as much during each switching cycle, and v sag greatly increases unless additional output capacitance is used. ii vv v vf l out in out in sw load valley(max) + = ? ? ? ? ? ? ? ( ) 2 pd (n resistance) - v v (i ) r l out in(max) load ds(on) 2 = ? ? ? ? ? ? ? ? ? ? ? ? ? ? 1 pd (n switching) h in(max) rss sw load gate 2 = () vcfi i pd (n resistance) v v (i ) r h out in load ds(on) 2 = ? ? ? ? ? ? dual step-down controllers with saturation protection, dynamic output, and linear regulator 40 ______________________________________________________________________________________
a reasonable minimum value for h is 1.5, but adjusting this up or down allows trade-offs between v sag , output capacitance, and minimum operating voltage. for a given value of h, the minimum operating voltage can be calculated as: where v drop1 is the parasitic voltage drop in the charge path (see the on-time one-shot section), t off(min) is from the electrical characteristics , and k is taken from table 3. the absolute minimum input voltage is calculated with h = 1. if the calculated v in(min) is greater than the required minimum input voltage, then operating frequency must be reduced or output capacitance added to obtain an acceptable v sag . if operation near dropout is anticipat- ed, calculate v sag to be sure of adequate transient response. dropout design example v out2 = 2.5v f sw = 355khz k = 3.0s, worst-case k min = 3.3s t off(min) = 500ns v drop1 = 100mv h = 1.5 calculating again with h = 1 and the typical k-factor value (k = 3.3s) gives the absolute limit of dropout: therefore, v in must be greater than 3.06v, even with very large output capacitance, and a practical input volt- age with reasonable output capacitance would be 3.47v. multi-output voltage settings (max1541 out1 only) while the main max1541 controller (out1) is optimized to work with applications that require two dynamic out- put voltages, it can produce three or more output volt- ages if required by using discrete logic or a dac. figure 15 shows an application circuit providing four voltage levels using discrete logic. switching resistors in and out of the resistor network changes the voltage at refin1. an edge-detection circuit is added to gen- erate a 1s pulse on gate to trigger the fault blanking and forced-pwm operation. when using pwm mode ( skip = v cc or open) on the main controller, the edge- detection circuit is only required if fault blanking is enabled. otherwise, leave od unconnected. active bus termination (max1541 out1 only) active-bus-termination power supplies generate a volt- age rail that tracks a set reference. they are required to source and sink current. ddr memory architecture requires active bus termination. in ddr memory archi- tecture, the termination voltage is set at exactly half the memory supply voltage. configure the main max1541 controller (out1) to generate the termination voltage using a resistive voltage-divider at refin1. in such an application, the main max1541 controller (out1) must be kept in pwm mode ( skip = v cc or open) in order for it to source and sink current. figure 16 shows the main max1541 controller configured as a ddr termina- tion regulator. connect gate and fblank to gnd when unused. v vv ns s v in(min) - = + ? ? ? ? ? ? = .. . . 25 01 1 1 500 33 306 v vv ns s v in(min) - = + ? ? ? ? ? ? = .. . . . 25 01 1 1 5 500 30 347 v vv ht k in(min) out drop1 off(min) - = + ? ? ? ? ? ? 1 max1540/max1541 dual step-down controllers with saturation protection, dynamic output, and linear regulator ______________________________________________________________________________________ 41 figure 15. multi-output voltage settings max1541 ref refin1 gnd gate r4 r3 a c1 r2 r1 b 1000pf 1.5k ? 1000pf 1.5k ?
max1540/max1541 voltage positioning in applications where fast load transients occur, the out- put voltage changes instantly by esr cout x ? i load . voltage positioning allows the use of fewer output capacitors for such applications, and maximizes the out- put voltage ac and dc tolerance window in tight-toler- ance applications. figure 17 shows the connection of out_ and fb_ in voltage-positioned and nonvoltage-positioned circuits. in nonvoltage-positioned circuits, the max1540/ max1541 regulate at the output capacitor. in voltage- positioned circuits, the max1540/max1541 regulate on the inductor side of the current-sense resistor. v out_ is reduced to: v out(vps) = v out(no load) - r sense x i load figure 18 shows the voltage-positioning transient response. pc board layout guidelines careful pc board layout is critical to achieving low switching losses and clean, stable operation. the switching power stage requires particular attention (figure 19). if possible, mount all the power compo- nents on the top side of the board, with their ground ter- minals flush against one another. follow these guidelines for good pc board layout: keep the high-current paths short, especially at the ground terminals. this practice is essential for sta- ble, jitter-free operation. keep the power traces and load connections short. this practice is essential for high efficiency. using thick copper pc boards (2oz vs. 1oz) can enhance full-load efficiency by 1% or more. correctly routing pc board traces is a difficult task that must be approached in terms of fractions of centimeters, where a single milliohm of excess trace resistance causes a measurable efficiency penalty. minimize current-sensing errors by connecting csp_ and csn_ directly across the current-sense resistor (r sense_ ). when trade-offs in trace lengths must be made, it is preferable to allow the inductor charging path to be made longer than the discharge path. for example, it is better to allow some extra distance between the input capacitors and the high-side mosfet than to allow distance between the inductor and the low- side mosfet or between the inductor and the out- put filter capacitor. route high-speed switching nodes (bst_, lx_, dh_, and dl_) away from sensitive analog areas (ref, fb_, csp_, csn_). layout procedure 1) place the power components first, with ground ter- minals adjacent (n l _ source, c in , c out _, and d l _ anode). if possible, make all these connections on the top layer with wide, copper-filled areas. 2) mount the controller ic adjacent to the low-side mosfet, preferably on the back side opposite n l _ and n h _ in order to keep lx_, gnd, dh_, and the dl_ gate-drive lines short and wide. the dl_ and dh_ gate traces must be short and wide (50 mils to 100 mils wide if the mosfet is 1in from the con- troller ic) to keep the driver impedance low and for proper adaptive dead-time sensing. dual step-down controllers with saturation protection, dynamic output, and linear regulator 42 ______________________________________________________________________________________ figure 16. active bus termination max1541 c out v in l c in od skip refin1 gate 10k ? 10k ? fblank v ddq = ddr memory supply voltage v tt = termination supply voltage gnd dl1 10nf dh1 lx1 csn1 csp1 r sense fb1 out1 v ddq v cc v tt = v ddq 2
max1540/max1541 dual step-down controllers with saturation protection, dynamic output, and linear regulator ______________________________________________________________________________________ 43 figure 17. voltage positioning max1540 max1541 c2 voltage-positioned output (v out(vps) ) c out input (v in ) +5v bias supply d bst c bst l1 r sense n h n l c in v cc v dd fb v out(vps) = v out(no load) - r sense i out csn_ out_ csp_ gnd dl_ dh_ bst_ v+ c1 r1 lx_ d l figure 18. voltage-positioning transient response b 50mv/div 1.4 1.4 a a. conventional converter b. voltage-positioned output voltage positioning the output v out esr voltage step (i step x r esr ) capacitive soar (dv/dt = i out /c out ) recovery capacitive sag (dv/dt = i out /c out ) i load
max1540/max1541 3) group the gate-drive components (bst_ diode and capacitor, v dd bypass capacitor) together near the controller ic. 4) make the dc-dc controller ground connections as shown in figures 1 and 12. this diagram can be viewed as having two separate ground planes: power ground, where all the high-power compo- nents go, and an analog ground plane for sensitive analog components. the analog ground plane and power ground plane must meet only at a single point directly at the ic. 5) connect the output power planes directly to the out- put filter capacitor positive and negative terminals with multiple vias. place the entire dc-dc converter circuit as close to the load as is practical. chip information transistor count: 8612 process: bicmos dual step-down controllers with saturation protection, dynamic output, and linear regulator 44 ______________________________________________________________________________________ figure 19. pc board layout inductor c out c out c in output input ground input output c out c in ground inductor high-power layout low-power layout max1540 bottom layer max1540 top layer dl lx dh dual n-channel mosfet kelvin-sense vias under the sense resistor (refer to evaluation kit) single n-channel mosfets via to v cc pin via to ref pin via to ref bypass capacitor via to v cc bypass capacitor via to power ground connect gnd and pgnd to the controller at one point only as shown connect the exposed pad to analog ground
max1540/max1541 dual step-down controllers with saturation protection, dynamic output, and linear regulator ______________________________________________________________________________________ 45 top view thin qfn 40 39 38 37 36 35 34 on1 on2 fblank csp1 csn1 fb1 out1 33 pgood1 11 12 13 14 15 16 17 refin1 od csp2 csn2 fb2 out2 pgood2 18 23 24 25 26 27 28 29 v+ ldoin v dd ldoout fbldo dl1 ldoon 8 7 6 5 4 3 2 ilim1 cc1 gate v cc ton lsat skip max1541 1 ovp/uvp 30 bst1 32 dh1 31 lx1 19 dh2 lx2 20 bst2 21 22 gnd dl2 10 9 ref ilim2 pin configurations (continued)
qfn thin.eps d2 (nd-1) x e e d c pin # 1 i.d. (ne-1) x e e/2 e 0.08 c 0.10 c a a1 a3 detail a 0.15 c b 0.15 c a document control no. 21-0140 package outline 16, 20, 28, 32l, qfn thin, 5x5x0.8 mm proprietary information approval title: c rev. 2 1 e2/2 e2 0.10 m c a b pin # 1 i.d. b 0.35x45 l d/2 d2/2 l c l c e e l c c l k k l l package information (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline info rmation, go to www.maxim-ic.com/packages .) max1540/max1541 dual step-down controllers with saturation protection, dynamic output, and linear regulator 46 ______________________________________________________________________________________
max1540/max1541 dual step-down controllers with saturation protection, dynamic output, and linear regulator ______________________________________________________________________________________ 47 2 2 21-0140 rev. document control no. approval proprietary information title: common dimensions exposed pad variations 1. dimensioning & tolerancing conform to asme y14.5m-1994. 2. all dimensions are in millimeters. angles are in degrees. 3. n is the total number of terminals. 4. the terminal #1 identifier and terminal numbering convention shall conform to jesd 95-1 spp-012. details of terminal #1 identifier are optional, but must be located within the zone indicated. the terminal #1 identifier may be either a mold or marked feature. 5. dimension b applies to metallized terminal and is measured between 0.25 mm and 0.30 mm from terminal tip. 6. nd and ne refer to the number of terminals on each d and e side respectively. 7. depopulation is possible in a symmetrical fashion. 8. coplanarity applies to the exposed heat sink slug as well as the terminals. 9. drawing conforms to jedec mo220. notes: 10. warpage shall not exceed 0.10 mm. c package outline 16, 20, 28, 32l, qfn thin, 5x5x0.8 mm package information (continued) (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline info rmation, go to www.maxim-ic.com/packages .)
max1540/max1541 dual step-down controllers with saturation protection, dynamic output, and linear regulator 48 ______________________________________________________________________________________ qfn thin 6x6x0.8 .eps e e l l a1 a2 a e/2 e d/2 d e2/2 e2 (ne-1) x e (nd-1) x e e d2/2 d2 b k k l c l c l c l c l c 1 2 21-0141 package outline 36,40l qfn thin, 6x6x0.8 mm package information (continued) (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline info rmation, go to www.maxim-ic.com/packages .)
max1540/max1541 dual step-down controllers with saturation protection, dynamic output, and linear regulator maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 ____________________ 49 ? 2003 maxim integrated products printed usa is a registered trademark of maxim integrated products. 8. coplanarity applies to the exposed heat sink slug as well as the terminals. 6. nd and ne refer to the number of terminals on each d and e side respectively. 5. dimension b applies to metallized terminal and is measured between 0.25 mm and 0.30 mm from terminal tip. 4. the terminal #1 identifier and terminal numbering convention shall conform to jesd 95-1 spp-012. details of terminal #1 identifier are optional, but must be located within the zone indicated. the terminal #1 identifier may be either a mold or marked feature. 9. drawing conforms to jedec mo220. 7. depopulation is possible in a symmetrical fashion. 3. n is the total number of terminals. 2. all dimensions are in millimeters. angles are in degrees. 1. dimensioning & tolerancing conform to asme y14.5m-1994. notes: max. min. nom. t3666-1 3.70 3.60 3.80 d2 max. nom. min. e2 codes pkg. exposed pad variations common dimensions 10. warpage shall not exceed 0.10 mm. t4066-1 4.00 4.10 4.20 4.00 4.20 4.10 3.80 3.70 3.60 c 2 2 21-0141 package outline 36, 40l qfn thin, 6x6x0.8 mm package information (continued) (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline info rmation, go to www.maxim-ic.com/packages .)

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